IBM S822LC, Technical Overview And Introduction

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Chapter 1. Architecture and technical description
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򐂰 Buffer Cache
By adopting this architecture, several decisions and processes regarding memory
optimizations are run outside the processor, saving bandwidth and allowing for faster
processor to memory communications. It also allows for more robust reliability, availability,
and serviceability (RAS). For more information about RAS, see 2.3, “Reliability, availability,
and serviceability” on page 33.
A detailed diagram of the memory riser card that is available for the Power S822LC server
and its location on the server are shown in Figure 1-12.
Figure 1-12 Memory riser card components and server location
The buffer cache is a L4 cache and is built on eDRAM technology (same as the L3 cache),
which has lower latency than regular SRAM. Each memory riser card has a buffer chip with
16 MB of L4 cache, and a fully populated Power S822LC server (two processors and eight
memory riser cards) has 128 MB of L4 cache. The L4 cache performs several functions that
have a direct impact on performance and brings a series of benefits for the Power S822LC
server:
򐂰 Reduces energy consumption by reducing the number of memory requests.
򐂰
Increases memory write performance by acting as a cache and by grouping several
random writes into larger transactions.
򐂰 Partial write operations that target the same cache block are “gathered” within the L4
cache before written to memory, becoming a single write operation.
򐂰
Reduces latency on memory access. Memory access for cached blocks has up to 55%
lower latency than non-cached blocks.
Connection to system backplane
DDR3 DIMM (4x)
Memory Buffer