IBM S822LC, Technical Overview And Introduction

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Chapter 1. Architecture and technical description
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Figure 1-9 shows a picture of the memory buffer, where you can see the 16 MB L4 cache and
processor links and memory interfaces.
Figure 1-9 Memory buffer chip
1.7.7 Hardware transactional memory
Transactional memory is an alternative to lock-based synchronization. It attempts to simplify
parallel programming by grouping read and write operations and running them as a single
operation. Transactional memory is like database transactions, where all shared memory
accesses and their effects are either committed all together or discarded as a group. All
threads can enter the critical region simultaneously. If there are conflicts in accessing the
shared memory data, threads try accessing the shared memory data again or are stopped
without updating the shared memory data. Therefore, transactional memory is also called a
lock-free synchronization
. Transactional memory can be a competitive alternative to
lock-based synchronization.
Transactional memory provides a programming model that makes parallel programming
easier. A programmer delimits regions of code that access shared data and the hardware
runs these regions atomically and in isolation, buffering the results of individual instructions,
and trying execution again if isolation is violated. Generally, transactional memory allows
programs to use a programming style that is close to coarse-grained locking to achieve
performance that is close to fine-grained locking.
Most implementations of transactional memory are based on software. The POWER8
processor-based systems provide a hardware-based implementation of transactional memory
that is more efficient than the software implementations and requires no interaction with the
processor core, therefore allowing the system to operate in maximum performance.
1.7.8 Coherent Accelerator Processor Interface
Coherent Accelerator Processor Interface (CAPI) defines a coherent accelerator interface
structure for attaching special processing devices to the POWER8 processor bus.
The CAPI can attach accelerators that have coherent shared memory access with the
processors in the server and share full virtual address translation with these processors,
which use a standard PCIe Gen3 bus.