IBM S822LC, Technical Overview And Introduction

Page: 25 / 80

Chapter 1. Architecture and technical description
11
Figure 1-6 on page 11 shows the areas of the processor that were modified to include the
NVLink and additional CAPI interface.
Figure 1-6 Areas modified on the POWER8 processor core
1.7.2 POWER8 processor core
The POWER8 processor core is a 64-bit implementation of the IBM Power Instruction Set
Architecture (ISA) Version 2.07 and has the following features:
򐂰 Multi-threaded design, which is capable of up to eight-way simultaneous multithreading
(SMT)
򐂰 32 KB, eight-way set-associative L1 instruction cache
򐂰 64 KB, eight-way set-associative L1 data cache
򐂰 Enhanced prefetch, with instruction speculation awareness and data prefetch depth
awareness
򐂰 Enhanced branch prediction, which uses both local and global prediction tables with a
selector table to choose the preferred predictor
򐂰 Improved out-of-order execution
򐂰 Two symmetric fixed-point execution units
򐂰 Two symmetric load/store units and two load units, all four of which can also run simple
fixed-point instructions
򐂰 An integrated, multi-pipeline vector-scalar floating point unit for running both scalar and
SIMD-type instructions, including the Vector Multimedia eXtension (VMX) instruction set
and the improved Vector Scalar eXtension (VSX) instruction set, and capable of up to
eight floating point operations per cycle (four double precision or eight single precision)
򐂰 In-core Advanced Encryption Standard (AES) encryption capability
2 C4 rows
added
x8 IOP
x8 PHB
NVLink support added in extended ES A-bus removed, NVLink added
Chip height:
2
nd
CAPP unit added, X2 removed