IBM p5 550, Technical Overview And Introduction

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Chapter 2. Architecture and technical overview
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򐂰 Double the SMP support. Changes have been made in the fabric, L2 and L3 controller,
memory controller, GX+ controller, and chip RAS to provide support for the QCM
(quad-core module) that allows the SMP system sizes to be double than is available in
POWER5 DCM-based servers. Current implementations support only a single
address loop.
򐂰 Several enhancements have been made in the memory controller for improved
performance. The memory controller is ready to support DDR2 667 MHz DIMMs in the
future.
򐂰
Enhanced redundancy in L1 Dcache, L2 cache, and L3 directory. Independent control of
the L2 cache and the L3 directory for redundancy to allow split-repair action has been
added. More wordline redundancy has been added in the L1 Dcache. In addition, Array
Built-In Self Test (ABIST) column repair for the L2 cache and the L3 directory has been
added.
2.2 Processor and cache
In the p5-550 or p5-550Q, the processors, associated L3 cache chips, and
memory DIMMs are packaged in processor cards. The processor and L3 cache
chips are packaged into processor modules. The p5-550 or p5-550Q use different
processor modules. The p5-550 uses a dual-core module (DCM) while the
p5-550Q uses an enhanced new packaging: the quad-core module (QCM).
2.2.1 p5-550Q quad-core module
The 4-core p5-550Q processor card contains a new quad-core module (QCM)
and the local memory storage subsystem for that QCM. Two dual core chips and
their associated L3 cache chips are packaged in the QCM. Figure 2-3 shows a layout view of
a QCM with associated memory.
Figure 2-3 p5-550Q 1.65 GHz QCM processor card with DDR2 memory socket layout view
The storage structure for the processor is a distributed memory architecture that
provides high-memory bandwidth. Each processor in the QCM can address all memory and
sees a single shared memory resource. In the QCM, one processor has direct
access to eight memory slots, controlled by two SMI-II chips, which are located in close
physical proximity to the processor modules. The other processor has access to
the same memory slots through the Vertical Fabric Bus.
QCM
2 x 16B
@825 MHz
SM
I-II
SM
I-II
1056 MHz
2 x 8B for read
2 x 2B for write
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
36 MB
L3 cache
2 x 16B
@825 MHz
36 MB
L3 cache
Core
1.65 GHz
Core
1.65 GHz
L3
ctrl
Mem
ctrl
Core
1.65 GHz
Core
1.65 GHz
2x 8B
@528 MHz
Mem
ctrl
Enhanced
distributed switch
Enhanced
distributed switch
L3
ctrl
GX+
Ctrl
GX+
Ctrl
GX+
Bus
1.9 MB
L2 cache
1.9 MB
L2 cache
QCM
2 x 16B
@825 MHz
SM
I-II
SM
I-II
1056 MHz
2 x 8B for read
2 x 2B for write
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
36 MB
L3 cache
2 x 16B
@825 MHz
36 MB
L3 cache
Core
1.65 GHz
Core
1.65 GHz
L3
ctrl
Mem
ctrl
Core
1.65 GHz
Core
1.65 GHz
2x 8B
@528 MHz
Mem
ctrl
Enhanced
distributed switch
Enhanced
distributed switch
L3
ctrl
GX+
Ctrl GX+
Ctrl
GX+
Ctrl GX+
Ctrl
GX+
Bus
1.9 MB
L2 cache
1.9 MB
L2 cache