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IBM System p5 550 and 550Q Technical Overview and Introduction
2.1 The processor
The processor capitalizes on all the enhancements brought by the POWER5
processors. For a detailed description of the POWER5 processor, refer to IBM
Eserver
p5
550 Technical Overview and Introduction, REDP-9113. Figure 2-2 shows a high-level view of
the processor.
Figure 2-2 processor
The CMOS10S technology in the processor uses a 90 nm fabrication process,
which enables:
Performance gains through faster clock rates
Physical size reduction (243 mm compared with 389 mm)
The processor is 37% smaller than the POWER5 processor. It consumes less
power and requires less cooling. Thus, you can use the processor in servers
where previously you could only use lower frequency chips due to cooling restrictions.
The design provides the following additional enhancements:
New pages sizes in ERAT and TLB. Two new pages sizes (64 KB and 16 GB), which were
recently added in the PowerPC® architecture.
New segment size in SLB. One new segment size (1 TB) recently added in PowerPC
architecture.
The TLB size has been doubled in the over the POWER5 processor. The TLB
in has 2048 entries.
Floating-point round to integer instructions. New instructions (frfin, frfiz, frfip, and frfim)
have been added to round floating-point numbers integers with the following rounding
modes: nearest, zero, integer plus, and integer minus.
Improved floating-point performance.
Lock performance enhancement.
Enhanced SLB read.
True Little-Endian mode. Support for the True Little-Endian mode as defined in the
PowerPC architecture.
Core
2.1 GHz
Core
2.1 GHz
1.9 MB L2
L3
Intf
Mem
Cntrl
GX+
Intf
SMP
Fabric
Bus
L3
Bus
Mem
Bus
GX+
Bus
Vertical
Fabric
Bus
Processor
Enhanced Distributed Switch
(Fabric Bus Controller)
Core
2.1 GHz
Core
2.1 GHz
Core
2.1 GHz
Core
2.1 GHz
1.9 MB L2
L3
Intf
Mem
Cntrl
GX+
Intf
SMP
Fabric
Bus
L3
Bus
Mem
Bus
GX+
Bus
Vertical
Fabric
Bus
Processor
Enhanced Distributed Switch
(Fabric Bus Controller)
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