HP E3494A, Installation And Service Manual

Page: 67 / 108

the JTAG connector at one end and the PowerPC microprocessor at the
other end. These signals are sensitive to crosstalk and must not be routed
along active signals such as clock lines on the target board.
The TDI, TCK, TMS and TRST signals must not be actively driven by the
target system when the debug port is being used.
The HRESET, SRESET and TRST signals from the JTAG connector must be
logically ORed with the HRESET, SRESET and TRST signals that connect to
the processor on the target system. They cannot be "dotted" or "wire-ORed"
on the board. The ORed signals should only reset the processor and no other
devices on the target system.
The HP processor probe adds about 40 pF to all target system signals routed
to the JTAG connector. This added capacitance may reduce the rise time of
the SRESET or the HRESET signal beyond the processor specifications. If
so, the target may need to increase the pull-up current on these signal lines.
Additional target requirements may be specified in the release notes in the
"readme" file on the provided floppy disk.
Target System Requirements for PowerPC 603e
Target systems which use any of the following modes of operation are not
currently supported:
•
Caches cannot be enabled for debug. A problem with the current CPU
chip corrupts the cache valid and LRU bits when debugging through the
JTAG port. The caches must be disabled for correct operation with the
HP E3494 PowerPC processor probe.
•
MMU when it is used for address translation. Only physical memory
addresses are accessible.
•
Little-endian byte ordering; memory display/modify is always in big-endian
mode. Byte swapping may be handled by the host software.
•
Address parity is not generated on external address bus operations.
Accesses to devices that check parity will fail.
•
The TLB entries cannot be accessed from the HP E3477 PowerPC probe.
•
If the processor runs to a branch to self instruction (op code 48000000H)
and the instruction is at an address ending with 04H or 0CH, the Probe will
not be able to soft stop the processor. If the processor doesn’t soft stop, it
will be "hard stopped" and an error message will be generated. Once the
Designing a Target System
Target System Requirements for PowerPC 603e
59