HP 5305 B, Operating And Service Manual

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Model 5305B
Theory of Operation
9E-4-14. In the Channel B mode, for example, the
operation is as follows. Once the sample rate runs down
and the INHIBIT line returns high, the next signal pulse
from U12A sets U17B. The High output from U16D(13)
arms the counter by allowing the CLOSE line to go
High. The arm signal also passes the 10 MHz clock
signal to the mainframe through U10A and U10B. The
mainframe responds by clocking U17A with a LOG 0
pulse, which sets the Q output Low and opens the Main
Gate. The signal now passes to the decade counter, U14,
where it is divided by 10. The data output of U14 feeds
U13C, which provides a 60/40 duty cycle of the divided
signal to level translators Q9 and Q10. The signal then
enters the main frame's counting assembly on the F1 line.
NOTE
U6, 12. 13, 14, 17, and 25 are ECL devices
that are connected to the +5V supply. They set
the logic states to ≈ 4.3V for a High and ≈
3.2V for a Low.
9E-4-15. The measurement ends when the count in the
mainframe's Time Base decade reaches its capacity.
The decade then outputs a TB OUT pulse. The LOG
pulse immediately following sets the MGFF and
disables the Main Gate, U13A. During the mea-
surement, the three-state data latch, U5, does not accept
any new input data. Its output, however, is enabled
periodically by the Low pulse from U4(15). Because of
the counting decade in the 5305B, U4 alters the Digital
Address codes so the digits are correctly placed in the
display. Therefore, the
Σ
4 output goes Low for one
count out of eight and switches the latch from its high
impedance state to the low impedance (active) state.
This occurs for each scan of the display. When the
measurement ends, the XFER line enables U4 and new data
enters the latch with the next clock pulse from U11(4).
9E-4-17. The Frequency Multiplier circuit contains a PLO
(Phase-Locked Oscillator) that is used when the RANGE
switch is set to the B 10 kHz MAX position. The PLO
multiplies the Channel B input frequency by 1000. which
means the display's count will be 1000 times higher than
normal. Thus, for a 51.234 Hz input and a 1 sec gate time,
the counter's display would be 00.051 kHz without the PLO
and 51.234 Hz with the PLO. The readout is corrected by
changing the annunciator from MHz to kHz or kHz to Hz.
The phase detector block diagram is shown in Figure 9E-
4-1.
9E-4-18. PHASE DETECTOR. The signal to be mea-
sured passes through the channel B amplifier and is applied
to pin 1 of U22, a phase/frequency detector. The other input
to U22 is the voltage-controlled oscillator's signal, which
has been divided by 1000 in U19, 20, and 21. U22 is a TTL
device with negative edge-triggered inputs and active low
outputs. Under normal, phase-locked operation, the negative
edges at the inputs occur at the same moment, and the two
outputs are high.
9E-4-19. Under these conditions, the two diodes following
the detector (also part of U22) are back-biased and pass no
current. Thus, no current enters the integrator amplifier,
U23, and its output voltage remains fixed.
Figure 9E-4-1. Phase Detector Block Diagram
9E-4-2
9E-4-16. Frequency Multiplier