MAN0974-14-EN_XL7_XL7P_UM
July 6, 2022
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9.3.8 Status Bits
There are three status bits (%I registers for each high-speed counter).
Overflow Flag
: This status bit turns high when the Accumulator “overflows”, it moves from
4,294,967,295 (-1 if Signed) to 0, this bit can be reset wit
h the “Output Reset Bit”. See Table
9.4.
Underflow Flag
: This status bit turns high when the Accumulator “underflows”, it moves from 0 to
4,294,967,295 (-
1 if Signed), this bit can also be reset with the “Output Reset Bit”.
NOTE
: For the Overflow and Underflow flag registers, if using some sort of counter that counts both up
and down, going over the threshold to go negative, triggers the underflow, and then going back over the
threshold back into positive numbers will trigger the positive register to go active.
High Speed Out
: This register will follow the high-speed output assigned to the counter, it is important
to note that this register is still populated within the scan time so the value in this register may not be
up to date depending on the timing of the output (it should be up to date within one scan).
