MAN0974-14-EN_XL7_XL7P_UM
July 6, 2022
Page 96 | 199
9.3.6 Register Match
Totalizer & Quadrature counter modes support a register match function. When the accumulator value
matches either the Match 1 or Match 2 value configured in the corresponding %AQ registers, a high-
speed output can Turn On, Turn Off, or Toggle. An internal %I register mirrors the output state whether
the high-speed output is configured or not. The output can be reset in program logic using the
corresponding %Q registers.
1.
2-Counter Mode has Register Match support for both counters.
2.
4-Counter Mode has Register Match support only for counters 1 and 2.
3.
The High-Speed Outputs are %Q1 for Counter 1 and %Q2 for Counter 2. They operate as high-
speed outputs, independent of the controller scan rate, when configured as
‘
HSC Output
’
in the
Digital Out/PWM configuration in Cscape.
4.
The High-Speed Output state reflects in the
status register “High Speed Out”
, e.g. %I1603 for
Counter 1 (the update speed of the status bit is scan rate dependent)
5.
The High-Speed Output can be reset through ladder with the assigned output, e.g. %Q1606 for
Counter 1
6.
Both Match 1 and Match 2 values will trigger the match function.
7.
If the output is already triggered by any Match register
while using ‘Turn On’ or ‘Turn Off’
modes, subsequent matches will not affect the output.
8.
If using ‘Toggle’ mode, every match of
either Match value will toggle the output to the opposite
state.
