manualshive.com logo in svg

Holtek HT46R003B, Manual, Page: 55 / 76

Share
Download
Holtek HT46R003B Manual Download Page 55

Rev. 1.00

5�

��ne 1�� �01�

Rev. 1.00 

55

��ne 1�� �01�

HT46R003B

Cost-Effective A/D 8-bit OTP MCU

HT46R003B

Cost-Effective A/D 8-bit OTP MCU

Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will 
be cleared automatically. This will prevent any further interrupt nesting from occurring. However, 
if other interrupt requests occur during this interval, although the interrupt will not be immediately 
serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the 
program is already in another interrupt service routine, the EMI bit should be set after entering the 
routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, 
even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service 
is desired, the stack must be prevented from becoming full.
When an interrupt request is generated it takes 2 or 3 instruction cycles before the program jumps to 
the interrupt vector. If the device is in the Sleep Mode and is woken up by an interrupt request then 
it will take 3 cycles before the program jumps to the interrupt vector.

Main

Program

Enable bit set?

Main

Program

Automatically Disable Interrupt 

Clear EMI & Request Flag

Wait for 2~3 Instruction Cycles

ISR Entry

...

...

RETI

(it will set EMI automatically)

Interrupt Request or

Interrupt Flag Set by Instruction

N

Y

Interrupt Flow

Interrupt Priority

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be 
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of 
simultaneous requests, the following table shows the priority that is applied. These can be masked 
by resetting the EMI bit.

Interrupt Source

Priority

Vector

External interr�pt

1

0�H

Timer/Event Counter overflow

�

08H

A/D converter complete

3

0CH

Time Base Overflow

�

10H

Summary of Contents for HT46R003B

Page 1: ...Cost Effective A D 8 bit OTP MCU HT46R003B Revision V1 00 Date June 19 2014 ...

Page 2: ...ning 10 Program Counter PC 11 Stack 12 Arithmetic and Logic Unit ALU 12 Program Memory 13 Structure 13 Special Vectors 13 Look up Table 13 Table Program Example 14 RAM Data Memory 15 Structure 15 Special Purpose Data Memory 15 Special Function Registers 17 Indirect Addressing Registers IAR0 IAR1 17 Memory Pointers MP0 MP1 17 Accumulator ACC 18 Program Counter Low Register PCL 18 Status Register ST...

Page 3: ...tures 33 Programming Considerations 34 Timer Event Counter 35 Configuring the Timer Event Counter Input Clock Source 35 Timer Register TMR 36 Timer Control Register TMRC 36 Timer Mode 37 Event Counter Mode 38 Pulse Width Capture Mode 38 Prescaler 39 PFD Function 40 I O Interfacing 40 Programming Considerations 40 Timer Program Example 41 Time Base 42 Pulse Width Modulator 42 PWM Operation 42 6 2 P...

Page 4: ...ase Interrupt 57 Interrupt Wake up Function 57 Programming Considerations 57 Application Circuits 58 Instruction Set 59 Introduction 59 Instruction Timing 59 Moving and Transferring Data 59 Arithmetic Operations 59 Logical and Rotate Operation 60 Branches and Control Transfer 60 Bit Operations 60 Table Read Operations 60 Other Operations 60 Instruction Set Summary 61 Table Conventions 61 Instructi...

Page 5: ...l components All instructions executed in one or two instruction cycles Table read instruction 63 powerful instructions 4 level subroutine nesting Bit manipulation instruction Peripheral Features Program Memory 1K 14 RAM Data Memory 64 8 Watchdog Timer function Up to 14 bidirectional I O lines 5 channel 12 bit A D Converter 1 channel 8 bit PWM External interrupt pin shared with I O pin One 8 bit p...

Page 6: ...rsatility of the device to suit for a wide range of the I O and A D control application possibilities such as industrial control consumer products and subsystem controllers etc Block Diagram 8 bit RISC MCU Core Time Base A D Converter I O Ports Interrupt Controller Reset Circuit Internal RC Oscillators 8 bit Timer Watchdog Timer Low Voltage Reset RAM Data Memory PWM Driver PFD Driver OTP Program M...

Page 7: ...ed pull up and wake up PWM CTRL0 CMOS PWM output PA5 AN4 PA5 PAPU PAWU ST CMOS General purpose I O Register enabled pull up and wake up AN4 ADPCR AN Analog input channel 4 PA6 INT PA6 PAPU PAWU ST CMOS General purpose I O Register enabled pull up and wake up INT INTC0 CTRL1 ST External interrupt input PA7 RES PA7 PAWU EXTRESB ST NMOS General purpose I O Register enabled wake up RES EXTRESB ST Rese...

Page 8: ... Max Unit VDD Conditions VDD Operating voltage fSYS 8MHz 2 3 5 5 V IDD Operating current HIRC on 3V No load fSYS 8MHz A D Converter disable 1 2 1 8 mA 5V 2 4 3 6 mA ISTB Standby current LIRC on 3V No load System halt 5 μA 5V 10 μA Standby current LIRC off 3V No load System halt 1 μA 5V 2 μA VIL Input Low Voltage for I O ports TMR INT 5V 0 1 5 V 0 0 2VDD V Input low voltage for RES pin 0 0 4VDD V V...

Page 9: ... 2 To maintain the accuracy of the internal HIRC oscillator frequency a 0 1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible A D Converter Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions AVDD Analog operating voltage VREF VDD 2 7 5 5 V VAD A D Input Voltage 0 AVDD VREF V DNL A D Differential Non l...

Page 10: ...addressed The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I O and A D system with maximum reliability and flexibility Clocking and Pipelining The main system clock derived from HIRC oscillator is subdivided into four internally generated non overlapping clocks T1 T4 The Pr...

Page 11: ...ram Counter For conditional skip instructions once the condition has been met the next instruction which has already been fetched during the present instruction execution is discarded and a dummy cycle takes its place while the correct instruction is obtained Program Counter High Byte of Program Low Byte of Program PC9 PC8 PCL7 PCL0 The lower byte of the Program Counter known as the Program Counte...

Page 12: ...owledge signal will be inhibited When the Stack Pointer is decremented by RET or RETI the interrupt will be serviced This feature prevents stack overflow allowing the programmer to use the structure more easily However when the stack is full a CALL subroutine instruction can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause un...

Page 13: ...rtain locations are reserved for the reset and interrupts The location 000H is reserved for use by the device reset for program initialisation After a device reset is initiated the program will jump to this location and begin execution Look up Table Any location within the Program Memory can be defined as a look up table where programmers can store fixed data To use the look up table the table poi...

Page 14: ...hould be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions If using the table read instructions the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main routine As a rule it is recommended that simultaneous use of the table read instructions should be avoided However in si...

Page 15: ...Memory for the device is the address 00H All microcontroller programs require an area of read write memory where temporary data can be stored and retrieved for use later It is this area of RAM memory that is known as General Purpose Data Memory This area of Data Memory is fully accessible by the user program for both reading and writing operations By using the SET m i and CLR m i instructions indi...

Page 16: ...5H PCL 06H TBLP 07H TBLH 08H WDTS 09H STATUS 0AH INTC0 0BH TMR 0CH TMRC 0DH INTC1 0EH 0FH PA 10H PAC 11H PAPU 12H PAWU 13H PB 14H PBC 15H PBPU 16H 17H 18H 19H CTRL0 1AH CTRL1 1BH WDTC 1CH 1DH ADPCR 1EH PWM0 1FH ADRL 20H ADRH 21H ADCR 22H ACSR 23H 24H EXTRESB 25H 3FH unused read as 00H Special Purpose Data Memory ...

Page 17: ...mented reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation Memory Pointers MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which t...

Page 18: ... only 8 bit wide only jumps within the current Program Memory page are permitted When such operations are used note that a dummy cycle will be inserted Status Register STATUS This 8 bit register contains the zero flag Z carry flag C auxiliary carry flag AC overflow flag OV power down flag PDF and watchdog time out flag TO These arithmetic logical operation and system management flags are used to r...

Page 19: ... 0 No overflow 1 An operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero flag 0 The result of an arithmetic or logical operation is not zero 1 The result of an arithmetic or logical operation is zero Bit 1 AC Auxiliary flag 0 No auxiliary carry 1 An operation results in a carry out of the low nibbles in addition or no borro...

Page 20: ... Unimplemented read as 0 Bit 5 PWMSEL PWM type selection 0 6 2 1 7 1 Bit 4 Unimplemented read as 0 Bit 3 PWMC I O or PWM selection 0 PA4 1 PWM Bit 2 PFDC I O or PFD selection 0 PB5 1 PFD Bit 1 0 Unimplemented read as 0 CTRL1 Register Bit 7 6 5 4 3 2 1 0 Name INTES1 INTES0 TBSEL1 TBSEL0 R W R W R W R W R W POR 1 0 0 0 Bit 7 6 INTES1 INTES0 External interrupt edge type selection 00 Disable 01 Rising...

Page 21: ...ccompany sections Internal RC Oscillator HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components The internal RC oscillator has the frequency of 8MHz Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuit is used to ensure that the influence of the power supply voltage temperature and process va...

Page 22: ... instruction The Data Memory contents and registers will maintain their present condition The WDT will be cleared and resume counting The I O ports will maintain their present condition In the status register the Power Down flag PDF will be set and the Watchdog time out flag TO will be cleared Standby Current Considerations As the main reason for entering the Sleep Mode is to keep the current cons...

Page 23: ...em is woken up by an interrupt then two possible situations may occur The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full in which case the program will resume execution at the instruction following the HALT instruction In this situation the interrupt which woke up the device will not be immediately serviced but will rather be serviced later when ...

Page 24: ... this specified internal clock period can vary with VDD temperature and process variations Watchdog Timer Control Registers WDTS Register Bit 7 6 5 4 3 2 1 0 Name WS2 WS1 WS0 R W R W R W R W POR 1 1 1 Bit 7 3 Unimplemented read as 0 Bit 2 0 WS2 WS0 WDT Time out period selection 000 28 fS 001 28 fS 010 210 fS 011 211 fS 100 212 fS 101 213 fS 110 214 fS 111 215 fS These three bits determine the divi...

Page 25: ... Timer clock source the Watchdog Timer will stop For systems that operate in noisy environments it s recommended to use the LIRC as the clock source The division ratio of the prescaler is determined by bits 0 1 and 2 of the WDTS register known as WS0 WS1 and WS2 If the Watchdog Timer internal clock source is selected and with the WS0 WS1 and WS2 bits of the WDTS register all set high the prescaler...

Page 26: ...ions being set Another reset exists in the form of a Low Voltage Reset LVR where a full reset similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold Reset Functions There are five ways in which a microcontroller reset can occur through events occurring both internally and externally Power on Reset The most fundamental and unavoidable re...

Page 27: ...ponent is added in environments where power line noise is significant External RES Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by software control using the register EXTRESB In this case of other reset the Program...

Page 28: ...is the same as a hardware RES pin reset except that the Watchdog time out flag TO will be set to 1 Note tRSTD is power on delay typical time 50ms WDT Time out Reset during Normal Operation Timing Chart Watchdog Time out Reset during Sleep Mode The Watchdog time out Reset during Sleep Mode is a little different from other kinds of reset Most of the conditions remain unchanged except that the Progra...

Page 29: ...LP x x x x x x x x uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH x x x x x x uu uuuu uu uuuu uu uuuu uu uuuu WDTS 1 1 1 1 1 1 1 1 1 1 1 1 uuu STATUS 0 0 x x x x uu uuuu 0 1 uuuu 1 u uuuu 1 1 uuuu INTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuu uuuu TMR x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x uuuu uuuu TMRC 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0...

Page 30: ...til the output latch is rewritten Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 I O Registers List Pull high Resistors Many product...

Page 31: ...r known as PAWU located in the Data Memory PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PAWU7 PAWU0 Port A bit 7 bit 0 wake up control 0 Disable 1 Enable I O Port Control Registers Each port has its own control register known as PAC PBC which control the input output configuration With this co...

Page 32: ... For this shared pin to be used as Timer Event Counter input the Timer Event Counter must be configured to be in the Event Counter or Pulse Width Capture Mode This is achieved by setting the appropriate bits in the Timer Event Counter Control Register The pin must also be set as input by setting the appropriate bit in the Port Control Register Pull high resistor options can also be selected using ...

Page 33: ... be properly setup If chosen as I O pins then full pull high resistor control remains however if used as A D inputs then any pull high resistor control associated with these pins will be automatically disconnected I O Pin Structures The accompanying diagrams illustrate the I O pin internal structures As the exact logical construction of the I O pin may differ from these drawings they are supplied ...

Page 34: ...e first programmed Selecting which pins are inputs and which are outputs can be achieved byte wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET m i and CLR m i instructions Note that when using these bit control instructions a read modify write operation takes place The microcontroller must fir...

Page 35: ... configured to come from the internal clock source In addition the timer clock source can also be configured to come from an external timer pin Configuring the Timer Event Counter Input Clock Source The Timer Event Counter clock source can originate from various sources an internal clock or an external pin The internal clock source is used when the timer is in the timer mode For the Timer Event Co...

Page 36: ...ed by the contents of their respective control register The Timer Control Register is known as TMRC It is the Timer Control Register together with its corresponding timer register that controls the full operation of the Timer Event Counter Before the timer can be used it is essential that the Timer Control Register is fully programmed with the right data to ensure its correct operation a process t...

Page 37: ...l Register must be set to the correct value as shown Bit7 Bit6 1 0 Control Register Operating Mode Select Bits for the Timer Mode In this mode the internal clock is used as the timer clock The timer input clock source is fSYS fSYS 4 or fLIRC However this timer clock source is further divided by a prescaler the value of which is determined by the bits TPSC2 TPSC0 in the Timer Control Register The t...

Page 38: ...sure that the pin is configured to operate as an event counter input pin two things have to happen The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer Event Counter in the Event Counting Mode The second is to ensure that the port control register configures the pin as an input It should be noted that in the event counting mode even if the microc...

Page 39: ...ived on the TMR pin As the enable bit has now been reset any further transitions on the external timer pin will be ignored The timer cannot begin further pulse width capture until the enable bit is set high again by the program In this way single shot pulse measurements can be easily made It should be noted that in this mode the Timer Event Counter is controlled by logical transitions on the exter...

Page 40: ...timer pin for its operation As this pin is a shared pin it must be configured correctly to ensure that it is set for use as a Timer Event Counter input pin This is achieved by ensuring that the mode selects bits in the Timer Event Counter control register either the event counter or pulse width capture mode Additionally the corresponding Port Control Register bit must be set high to ensure that th...

Page 41: ...r Event Counter overflow will also generate a wake up signal if the device is in a Power down condition This situation may occur if the Timer Event Counter is in the Event Counting Mode and if the external signal continues to change state In such a case the Timer Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power down con...

Page 42: ...ary to write the required value into the PWM register and select the required mode set and on off control using the CTRL0 register the subdivision of the waveform into its sub modulation cycles is implemented automatically within the microcontroller hardware The PWM clock source fS comes from the system clock fSYS fSYS 4 or fLIRC This method of dividing the original modulation cycle into a further...

Page 43: ...cycle 0 modulation cycle 1 denoted as i in the table Each one of these two sub cycles contains 128 clock cycles In this mode a modulation frequency increase of two is achieved The 8 bit PWM register value which represents the overall duty cycle of the PWM waveform is divided into two groups The first group which consists of bit 1 bit 7 is denoted here as the DC value The second group which consist...

Page 44: ...ing bit in the output data register PA 4 will enable the PWM data to appear on the pin Writing a zero value will disable the PWM output function and force the output low In this way the Port data output registers can be used as an on off control for the PWM function Note that if the CTRL0 register has selected the PWM function but a high value has been written to its corresponding bit in the PAC c...

Page 45: ...2 bit digital value The accompanying block diagram shows the overall internal structure of the A D converter together with its associated registers A D Converter Structure A D Converter Data Registers ADRL ADRH The device which has an internal 12 bit A D converter require two data registers a high byte register known as ADRH and a low byte register known as ADRL After the conversion process takes ...

Page 46: ...in namely one of the AN0 AN3 analog inputs will be set as analog inputs Note that if the PCRn bit is set to zero then the corresponding pin on PA5 PA3 PA0 will be set as a normal I O pin the analog input channels will be all disabled and the A D converter circuitry will be powered off The ADPCR control register contains the PCR4 PCR0 bits which determine which pins on PA0 PA3 PA5 are used as analo...

Page 47: ... fSYS 8 010 fSYS 32 011 Undefined 100 fSYS 101 fSYS 4 110 fSYS 16 111 Undefined These three bits are used to select the clock source for the A D converter ADPCR Register Bit 7 6 5 4 3 2 1 0 Name PCR4 PCR3 PCR2 PCR1 PCR0 R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 5 Unimplemented read as 0 Bit 4 PCR4 Define PA5 is A D input or not 0 Not A D input 1 A D input AN4 Bit 3 PCR3 Define PA3 is A D input o...

Page 48: ...m clock fSYS is first divided by a division ratio the value of which is determined by the ADCS2 ADCS1 and ADCS0 bits in the ACSR register The A D converter overall on off control is a function of both the ADONB bit in the ACSR register and the PCR4 PCR0 bits in the ADPCR register as shown in the table Either the ADONB bit cleared to zero or the PCR4 PCR0 bits set to a zero value will switch off th...

Page 49: ...ut in the I O port control registers to enable the A D input as when the PCR4 PCR0 bits enable an A D input the status of the port control register will be overridden Summary of A D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A D conversion process Step 1 Select the required A D conversion clock by correctly programming bits ADCS2...

Page 50: ...nverter After an A D conversion process has been initiated by the application program the microcontroller internal hardware will begin to carry out the conversion during which time the program can continue with other functions The time taken for the A D conversion is 16tAD where tAD is equal to the A D clock period Programming Considerations When programming the special attention must be given to ...

Page 51: ...ete whereas in the second example the A D interrupt is used to determine when the conversion is complete Example using an EOCB polling method to detect the end of conversion clr ADE disable A D Converter interrupt mov a 00000001B mov ACSR a select fSYS 8 as A D clock and ADONB 0 mov a 00011111B mov ADPCR a setup ADCR register to configure I O Port as A D inputs mov a 00000000B mov ADCR a select AN...

Page 52: ...able A D Converter interrupt set EMI enable global interrupt A D Converter interrupt service routine ADC_ISR mov acc_stack a save ACC to user defined memory mov a STATUS mov status_stack a save STATUS to user defined memory mov a ADRL read low byte conversion result value mov adrl_buffer a save result to user defined register mov a ADRH read high byte conversion result value mov adrh_buffer a save...

Page 53: ...sing registers INTC0 and INTC1 By controlling the appropriate enable bits in the register each individual interrupt can be enabled or disabled Also when an interrupt occurs the corresponding request flag will be set by the microcontroller The global enable flag cleared to zero will disable all interrupts Function Enable Bit Request Flag Global EMI INT Pin INTE INTF Timer TE TF A D Converter ADE AD...

Page 54: ...be the value of the corresponding interrupt vector The microcontroller will then fetch its next instruction from this interrupt vector The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine Here is located the code to control the appropriate interrupt The interrupt service routine must be terminat...

Page 55: ... becoming full When an interrupt request is generated it takes 2 or 3 instruction cycles before the program jumps to the interrupt vector If the device is in the Sleep Mode and is woken up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector Main Program Enable bit set Main Program Automatically Disable Interrupt Clear EMI Request Flag Wait for 2 3 In...

Page 56: ...vector at location 04H will take place When the interrupt is serviced the external interrupt request flag INTF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts Note that any pull high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input Timer Event Counter Interrupt For a Timer Event Counter i...

Page 57: ...on Programming Considerations By disabling the relevant interrupt enable bits a requested interrupt can be prevented from being serviced however once an interrupt request flag is set it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program It is recommended that programs do not use the C...

Page 58: ...tive A D 8 bit OTP MCU Application Circuits R E S P A 7 V D D V S S 0 1 F V D D 0 1 1 F 1 0 k 1 0 0 k 3 0 0 0 0 1 F 1 N 4 1 4 8 P A 0 A N 0 P A 1 A N 1 P A 2 A N 2 P A 3 A N 3 P A 4 P W M P A 5 A N 4 P A 6 I N T P B 0 P B 3 P B 4 T M R P B 5 P F D ...

Page 59: ...to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one cycle ...

Page 60: ...instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of ce...

Page 61: ...te Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x Logical AND immediate...

Page 62: ...ine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDC m Read table current page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set Data Memory 1Note None CLR WD...

Page 63: ...or and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data in...

Page 64: ...PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing CLR WDT2 will have no...

Page 65: ...is instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC Description Data in t...

Page 66: ... ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affected flag s Z OR A x...

Page 67: ...Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the specified Data Memory a...

Page 68: ...A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC ACC m C Affected fl...

Page 69: ...program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents remain unchanged As thi...

Page 70: ... interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is...

Page 71: ...a Memory Description The low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation Th...

Page 72: ...ntervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of Packing Materials...

Page 73: ...Nom Max A 0 780 0 790 0 800 B 0 240 0 250 0 280 C 0 115 0 130 0 195 D 0 115 0 130 0 150 E 0 014 0 018 0 022 F 0 045 0 060 0 070 G 0 1 BSC H 0 300 0 310 0 325 I 0 430 Symbol Dimensions in mm Min Nom Max A 19 81 20 07 20 32 B 6 10 6 35 7 11 C 2 92 3 30 4 95 D 2 92 3 30 3 81 E 0 36 0 46 0 56 F 1 14 1 52 1 78 G 2 54 BSC H 7 62 7 87 8 26 I 10 92 ...

Page 74: ...92 19 43 19 94 B 6 99 7 24 7 49 C 3 05 3 43 3 81 D 2 79 3 30 3 81 E 0 36 0 46 0 56 F 1 14 1 27 1 52 G 2 54 BSC H 7 62 7 87 8 26 I 10 92 Fig 2 Type2 Symbol Dimensions in inch Min Nom Max A 0 735 0 755 0 775 B 0 240 0 250 0 280 C 0 115 0 130 0 195 D 0 115 0 130 0 150 E 0 014 0 018 0 022 F 0 045 0 060 0 070 G 0 1 BSC H 0 300 0 310 0 325 I 0 430 Symbol Dimensions in mm Min Nom Max A 18 67 19 18 19 69 ...

Page 75: ...nsions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 390 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 31 0 51 C 9 9 BSC D 1 75 E 1 27 BSC F 0 10 0 25 G 0 40 1 27 H 0 10 0 25 α 0 8 ...

Page 76: ...d solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reserves...

Reviews:

No comments