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HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer TMR
pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode
Select bit pair, TM1/TM0, in the Timer Control Register must be set to the correct value as shown.
Bit7
Bit6
0
1
Control Register Operating Mode Select Bits for the Timer Mode
In this mode, the external timer TMR pin, is used as the Timer/Event Counter clock source, however
it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been
set, the enable bit TON, which is bit 4 of the Timer Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit, TEG, which is bit 3 of the Timer Control
Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a
low to high transition. If the TEG is high, the counter will increment each time the external timer pin
receives a high to low transition. When it is full and overflows, an interrupt signal is generated and
the Timer/Event Counter will reload the value already loaded into the preload register and continue
counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable
bit in the corresponding Interrupt Control Register. It is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as
an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode
Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting
Mode. The second is to ensure that the port control register configures the pin as an input. It should
be noted that in the event counting mode, even if the microcontroller is in the Sleep Mode, the
Timer/Event Counter will continue to record externally changing logic events on the timer input
TMR pin. As a result when the timer overflows it will generate a timer interrupt and corresponding
wake-up source.
Event Counter Mode Timing Chart (TEG=1)
Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses
applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, TM1/
TM0, in the Timer Control Register must be set to the correct value as shown.
Bit7
Bit6
1
1
Control Register Operating Mode Select Bits for the Pulse Width Capture Mode
In this mode the internal clock, f
SYS
, f
SYS
/4 or f
LIRC
is used as the internal clock for the 8-bit Timer/
Event Counter. However, the clock source, f
SYS
, for the 8-bit timer is further divided by a prescaler,
the value of which is determined by the Prescaler Rate Select bits TPSC2~TPSC0, which are bit
2~0 of the Timer Control Register, After other bits in the Timer Control Register have been set, the
enable bit TON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/
Event Counter, however it will not actually start counting until an active edge is received on the
external timer pin.