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HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
If the Active Edge Select bit TEG which is bit 3 of the Timer Control Register is low, once a high
to low transition has been received on the external timer pin, the Timer/Event Counter will start
counting until the external timer pin returns to its original high level. At this point the enable bit will
be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge
Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has
been received on the external timer pin and stop counting when the external timer pin returns to its
original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event
Counter will stop counting. It is important to note that in the pulse width capture mode, the enable
bit is automatically reset to zero when the external control signal on the external timer pin returns
to its original level, whereas in the other two modes the enable bit can only be reset to zero under
program control.
The residual value in the Timer/Event Counter, which can now be read by the program, therefore
represents the length of the pulse received on the TMR pin. As the enable bit has now been reset,
any further transitions on the external timer pin will be ignored. The timer cannot begin further pulse
width capture until the enable bit is set high again by the program. In this way, single shot pulse
measurements can be easily made. It should be noted that in this mode the Timer/Event Counter is
controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/
Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter
will reload the value already loaded into the preload register and continue counting. The interrupt
can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding
Interrupt Control Register, it is reset to zero. As the TMR pin is shared with an I/O pin, to ensure
that the pin is configured to operate as a pulse width capture pin, two things have to be implemented.
The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the
Timer/Event Counter in the pulse width capture mode, the second is to ensure that the port control
register configure the pin as an input.
Pulse Width Capture Mode Timing Chart (TEG=0)
Prescaler
Bits TPSC2~TPSC0 of the TMRC register can be used to define a division ratio for the internal
clock source of the Timer/Event Counter enabling longer time out periods to be set.