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Holtek BS86DH12C Manual Download Page 89

Rev. 1.00

88

October 26, 2018

Rev. 1.00 

89

October 26, 2018

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Counter Value

CCRP

CCRA

CTnON

CTnPAU

CTnPOL

CCRP Int. 

Flag CTMnPF

CCRA Int. 

Flag CTMnAF

CTMn O/P Pin 

(CTnOC=1)

Time

Counter cleared by 

CCRA

Pause

Resume

Counter Stop if 

CTnON bit low

Counter Reset when 

CTnON returns high

PWM Duty Cycle 

set by CCRP

PWM resumes 

operation

Output controlled by 

other pin-shared function

Output Inverts

when CTnPOL = 1

PWM Period set by CCRA

CTMn O/P Pin 

(CTnOC=0)

CTnDPX = 1; CTnM [1:0] = 10

PWM Output Mode – CTnDXP=1 (n=0~1)

Note: 1. Here CTnDPX=1 – Counter cleared by CCRA

2. A counter clear sets the PWM Period
3. The internal PWM function continues even when CTnIO[1:0]=00 or 01
4. The CTnCCLR bit has no influence on PWM operation

Summary of Contents for BS86DH12C

Page 1: ...High Voltage Touch A D Flash MCU with HVIO BS86DH12C Revision V1 00 Date October 26 2018 ...

Page 2: ...haracteristics LXT 17 Operating Frequency Characteristic Curves 17 System Start Up Time Characteristics 18 Input Output Characteristics 19 Memory Characteristics 19 LVD LVR Electrical Characteristics 20 A D Converter Electrical Characteristics 20 Internal Reference Voltage Characteristics 21 High Voltage I O Electrical Characteristics 21 Voltage Detector Electrical Characteristics 21 High Voltage ...

Page 3: ...TATUS 36 EEPROM Data Memory 38 EEPROM Data Memory Structure 38 EEPROM Registers 38 Reading Data from the EEPROM 39 Writing Data to the EEPROM 40 EEPROM Interrupt 40 Programming Considerations 40 Oscillators 42 Oscillator Overview 42 System Clock Configurations 42 Internal High Speed RC Oscillator HIRC 43 Internal 32kHz Oscillator LIRC 43 External 32 768 kHz Crystal Oscillator LXT 43 Operating Mode...

Page 4: ...terrupts 78 TM External Pins 78 Programming Considerations 79 Compact Type TM CTM 80 Compact Type TM Operation 80 Compact Type TM Register Description 81 Compact Type TM Operation Modes 84 Periodic Type TM PTM 90 Periodic TM Operation 90 Periodic Type TM Register Description 90 Periodic Type TM Operation Modes 95 Analog to Digital Converter 104 A D Overview 104 A D Converter Register Description 1...

Page 5: ... Communication 133 I2 C Time out Control 137 UART Interface 138 UART External Pins 139 UART Data Transfer Scheme 139 UART Status and Control Registers 139 Baud Rate Generator 145 UART Setup and Control 145 UART Transmitter 146 UART Receiver 148 Managing Receiver Errors 149 UART Interrupt Structure 150 UART Power Down and Wake up 151 Low Voltage Detector LVD 152 LVD Register 152 LVD Operation 153 I...

Page 6: ...on 166 Instruction Timing 166 Moving and Transferring Data 166 Arithmetic Operations 166 Logical and Rotate Operation 167 Branches and Control Transfer 167 Bit Operations 167 Table Read Operations 167 Other Operations 167 Instruction Set Summary 168 Table Conventions 168 Extended Instruction Set 170 Instruction Definition 172 Extended Instruction Definition 181 Package Information 188 20 pin SOP 3...

Page 7: ... 16 Data Memory 512 8 True EEPROM Memory 64 8 12 touch key functions fully integrated without requiring external components Watchdog Timer function 22 bidirectional I O lines 6 bidirectional High Voltage I O lines with short circuit protection function Programmable I O port source current and sink current for LED driving applications Single external interrupt line shared with I O pin Multiple Time...

Page 8: ...n coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments A full choice of external low internal high and low speed oscillators are provided including fully integrated system oscillators which require no external components for its implementation The ability to operate and switch dynamically between a range of operati...

Page 9: ...unction PA0 PA7 PB0 PB7 Port B Driver PC0 PC5 Port C Driver MUX Clock System HT8 MCU Core Time Base Interrupt Controller INT Pin Shared With Port C Reset Circuit Pin Shared With Port A LIRC 32kHz HIRC 8 12 16MHz MUX LXT XT1 XT2 Stack 8 Level RAM 512 8 ROM 8K 16 Watchdog Timer EEPROM 64 8 LVR LVD OCPAO VOCPAO _ Pin Shared With Port A B 8 bit DAC _ 8 bit DAC OPA Digital Peripherals Touch Key Module ...

Page 10: ...1 PB2 SCL AN6 KEY9 PC5 PC4 PB7 CTP1B AN5 OVPCOUT PB6 CTP1 AN4 OCPAO PC1 INT PTPB OVPI1 KEY12 PC0 PTP OVPI0 KEY11 PB3 SDA AN7 KEY10 PC3 CTP0 SDA TX PC2 CTP1 SCL RX PA2 TX CTP1B OCPI ICPCK OCDSCK PA0 RX CTP1 OCPVR ICPDA OCDSDA PA6 CTCK1 PTPI CTP0 PTPB XT1 VDD VLDO AVDD VSS AVSS IOVSS HVSS PA7 CTCK0 PTCK PTP XT2 NC NC NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24...

Page 11: ... CMOS CTM1 output OCPVR PAS0 AN OCP D A converter reference voltage input ICPDA ST CMOS ICP data address OCDSDA ST CMOS OCDS data address for EV chip only PA1 PTCK SCL OVPI1 KEY3 PA1 PAPU PAWU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up PTCK PAS0 IFS1 ST PTM clock input SCL PAS0 IFS0 ST NMOS I2 C clock line OVPI1 PAS0 AN OVP input 1 KEY3 PAS0 NSI Touch key input PA2 TX CT...

Page 12: ...K PAS1 IFS1 ST PTM clock input PTP PAS1 CMOS PTM output XT2 PAS1 LXT LXT oscillator pin PB0 RX CTCK0 OCPI KEY1 PB0 PBPU PBS0 ST CMOS General purpose I O Register enabled pull up RX PBS0 IFS0 ST UART data receive pin CTCK0 PBS0 IFS1 ST CTM0 clock input OCPI PBS0 AN OCP input KEY1 PBS0 NSI Touch key input PB1 TX CTCK1 OVPI0 KEY2 PB1 PBPU PBS0 ST CMOS General purpose I O Register enabled pull up TX P...

Page 13: ...ter external input channel OVPCOUT PBS1 CMOS OVP comparator output PC0 PTP OVPI0 KEY11 PC0 PCPU PCS0 ST CMOS General purpose I O Register enabled pull up PTP PCS0 CMOS PTM output OVPI0 PCS0 AN OVP input 0 KEY11 PCS0 NSI Touch key input PC1 INT PTPB OVPI1 KEY12 PC1 PCPU PCS0 ST CMOS General purpose I O Register enabled pull up INT PCS0 INTC0 INTEG ST External interrupt input PTPB PCS0 CMOS PTM inve...

Page 14: ...ut CMOS CMOS output NMOS NMOS output AN Analog signal NSI Non standard input LXT Low frequency crystal oscillator Absolute Maximum Ratings Supply Voltage VCC VSS 0 3V to 10 0V Supply Voltage VDD VSS 0 3V to VSS 6 0V High Voltage Input Voltage VSS 0 3V to VCC 0 3V Input Voltage VSS 0 3V to VDD 0 3V Storage Temperature 50 C to 125 C Operating Temperature 40 C to 85 C High Voltage IOH Total 150mA IOH...

Page 15: ...rating Current Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions IDD SLOW Mode LIRC 5V fSYS fLIRC 32kHz LDO current consumption included 180 200 μA SLOW Mode LXT 5V fSYS fLXT 32768Hz LDO current consumption included 180 200 μA FAST Mode HIRC 5V fSYS fHIRC 8MHz LDO current consumption included 1 6 2 4 mA fSYS fHIRC 12MHz LDO current consumption included 2 4 3 ...

Page 16: ...uction executed thus stopping all instruction execution A C Characteristics For data in the following tables note that factors such as oscillator type operating voltage operating frequency and temperature etc can all exert an influence on the measured values High Speed Internal Oscillator HIRC Frequency Accuracy During the program writing operation the writer will trim the HIRC oscillator at a use...

Page 17: ...Oscillator Characteristics LIRC Symbol Parameter Test Conditions Min Typ Max Unit VDD Temp fLIRC LIRC Frequency 4 5V 5 5V 25 C 10 32 10 kHz 40 C 85 C 50 32 60 tSTART LIRC Start Up Time 25 C 500 μs External Low Speed Oscillator Characteristics LXT Ta 25 C C1 C2 10pF RP 10MΩ C1 C2 and RP are external components CL 7pF ESR 30kΩ Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions fLXT LXT...

Page 18: ...30 48 72 ms System Reset Delay Time LVRC WDTC RSTC Software Reset System Reset Delay Time Reset Source from WDT Overflow 10 16 24 ms tSRESET Minimum Software Reset Width to Reset 45 90 180 μs Note 1 For the System Start up time values whether fSYS is on or off depends upon the mode type and the chosen fSYS system oscillator Details are provided in the System Operating Modes section 2 The time unit...

Page 19: ...Current 5V VIN VDD or VIN VSS 1 μA tTCK TM Clock Input Pin Minimum Pulse Width 0 3 μs tTPI TM Capture Input Pin Minimum Pulse Width 0 3 μs tINT External Interrupt Minimum Pulse Width 10 μs Note The RPH internal pull high resistance value is calculated by connecting to ground and enabling the input pin with a pull high resistor and then measuring the pin current at the specified supply voltage leve...

Page 20: ...O Stable Time For LVR enable VBGEN 0 LVD off on 15 μs tLVR Minimum Low Voltage Width to Reset 120 240 480 μs tLVD Minimum Low Voltage Width to Interrupt 60 120 240 μs A D Converter Electrical Characteristics Ta 40 C 85 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDD A D Converter Operating Voltage 4 5 5 5 V VADI A D Converter Input Voltage 0 VREF V VREF A D Converter Referen...

Page 21: ...e VDET1 10 V VIH Input High Voltage for High Voltage I O Ports 0 6VIN VIN V VIL Input Low Voltage for High Voltage I O Ports 0 0 3VIN V IOH Source Current for High Voltage I O Ports VOH 0 9 VIN VIN 10V 40 70 mA IOL Sink Current for High Voltage I O Ports VOL 0 1 VIN VIN 10V 50 80 mA tSF Short Circuit Flag Response Time SFRTC 0 Ta 25 C 2 3 ms SFRTC 0 Ta 40 C 85 C 1 5 3 9 SFRTC 1 Ta 25 C 1 0 1 5 SFR...

Page 22: ...Ω 3kΩ VCC1O R12 R11 R12 VCC1 0 2VCC1 Divider 2 R21 R22 4 1 12kΩ 3kΩ VCC2O R22 R21 R22 VCC2 0 2VCC2 Low Dropout Regulator Electrical Characteristics CLOAD 10μF 0 1μF VIN VOUT 1V Ta 25 C unless otherwise specified Symbol Parameter Test Conditions Min Typ Max Unit VIN Conditions VIN Input Voltage 6 10 V VOUT Output Voltage Ta 25 C ILOAD 1mA VOUT 5 0V 2 5 0 2 V Ta 40 C 85 C ILOAD 1mA VOUT 5 0V 5 5 0 5...

Page 23: ...s PD TJ MAX Ta θJA 2 Dropout voltage is defined as the input voltage minus the output voltage that produces a 2 change in the output voltage from the value at appointed VIN 3 Ripple rejection ratio measurement circuit RR 20 log ΔVIN ΔVOUT 0 33μF 1 3 2 10 1μF RL Output GND LDO VIN VOUT AC 4 Application information for LDO load capacitor selection for stability Recommended Output Capacitor Ta 25 C S...

Page 24: ...ximum Output Voltage Range 5V VSS 0 1 VDD 0 1 V Ga PGA Gain Accuracy 5V All gains 5 5 VREF D A Converter Reference Voltage 5V OCPVRS 1 2 VDD V DNL Differential Non linearity 5V DAC VREF VDD 1 1 LSB INL Integral Non linearity 5V DAC VREF VDD 1 5 1 5 LSB OVP Electrical Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions IOVP Operating Current 5V OVPEN 1 DAC VREF ...

Page 25: ...sions etc The internal data path is simplified by moving data through the Accumulator and the ALU Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I O and A D control s...

Page 26: ...ed by one each time an instruction is executed except for instructions such as JMP or CALL that demand a jump to a non consecutive Program Memory address Only the lower 8 bits known as the Program Counter Low Register are directly addressable by the application program When executing instructions requiring jumps to non consecutive addresses such as a jump instruction a subroutine call interrupt or...

Page 27: ...re more easily However when the stack is full a CALL subroutine instruction can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching If the stack is overflow the first Program Counter save in the stack will be lost Stack Pointer Stack Level 2 Stack Level 1 Stack Level 3 Stack Level 8 Program Memory...

Page 28: ...000H 0004H n00H nFFH 1FFFH 0034H Program Memory Structure Special Vectors Within the Program Memory certain locations are reserved for the reset and interrupts The location 0000H is reserved for use by the device reset for program initialisation After a device reset is initiated the program will jump to this location and begin execution Look up Table Any location within the Program Memory can be d...

Page 29: ... equal to zero will be transferred to the TBLH register automatically when the TABRD m instruction is executed Because the TBLH register is a read write register and can be restored care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions If using the table read instructions the Interrupt Service Routines may change the value ...

Page 30: ...he latest program releases without removal and re insertion of the device Holtek Writer Pins MCU Programming Pins Pin Description ICPDA PA0 Programming Serial Data Address ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory can be programmed serially in circuit using this 4 wire interface Data is downloaded and uploaded serially on a single pin with an additional lin...

Page 31: ...Chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground Data Memory The Data Memory is a volatile area of 8 bit wide RAM internal memory and is the location where temporary information is stored Categorized into two types the first of these is an area of RAM where special function registers are located These registers have fixed locations and are necessary for correct operation of the d...

Page 32: ...ns and extended instructions is that the data memory address m in the extended instructions has 10 valid bits for the device the high byte indicates a sector and the low byte indicates a specific address General Purpose Data Memory All microcontroller programs require an area of read write memory where temporary data can be stored and retrieved for use later It is this area of RAM memory that is k...

Page 33: ...M2ROL TKM216DH TKM216DL TKM1C1 TKM1C0 TKM1ROH TKM1ROL TKM116DH TKM116DL TKM0C1 TKM0C0 TKM0ROH TKM0ROL TKM016DH TKM016DL TKC1 TK16DH TK16DL TKC0 TKTMR RSTC PWRDET PDOM OVPDA OVPC2 OVPC1 OVPC0 EEC OCPC0 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 59H 58H 5BH 5AH 5DH 5CH 5FH 53H 54H 55H 56H 57H 5EH 60H 61H 62H 69H 68H 6BH 6AH 6DH 6CH 6FH 6EH 63H 64H 65H 66H 67H 70H 71H...

Page 34: ...H and writing to the registers will result in no operation Memory Pointers MP0 MP1L MP1H MP2L MP2H Five Memory Pointers known as MP0 MP1L MP1H MP2L MP2H are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect...

Page 35: ...e m data to acc lsub a m 1 compare m and m 1 data snz c m m 1 jmp continue no lmov a m yes exchange m and m 1 data mov temp a lmov a m 1 lmov m a mov a temp lmov m 1 a continue Note here m is a data memory address located in any data memory sectors For example m 1F0H it indicates address 0F0H in Sector 1 Accumulator ACC The Accumulator is central to the operation of any microcontroller and is clos...

Page 36: ...o record the status and operation of the microcontroller With the exception of the TO and PDF flags bits in the status register can be altered by instructions like most other registers Any data written into the status register will not change the TO or PDF flag In addition operations related to the status register may give different results due to the different instruction operations The TO flag c...

Page 37: ...ed by the previous operation CZ flag and current operation zero flag For other instructions the CZ flag will not be affected Bit 5 TO Watchdog Time out flag 0 After power up or executing the CLR WDT or HALT instruction 1 A watchdog time out occurred Bit 4 PDF Power down flag 0 After power up or executing the CLR WDT instruction 1 By executing the HALT instruction Bit 3 OV Overflow flag 0 No overfl...

Page 38: ...y Read and Write operations to the EEPROM are carried out in single byte operations using an address and a data register in Sector 0 and a single control register in Sector 1 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address register EEA the data register EED and a single control register EEC As both the EEA and EED registers ar...

Page 39: ...read operations are carried out Clearing this bit to zero will inhibit Data EEPROM read operations Bit 0 RD EEPROM Read Control 0 Read cycle has finished 1 Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle This bit will be automatically reset to zero by the hardware after the read cycle has finished Setting this b...

Page 40: ...e operations Also at power on the Memory Pointer high byte register MP1H or MP2H will be reset to zero which means that Data Memory Sector 0 will be selected As the EEPROM control register is located in Sector 1 this adds a further measure of protection against spurious write operations During normal program operation ensuring that the Write Enable bit in the control register is cleared will safeg...

Page 41: ... required CLR MP1H MOV A EED move read data to register MOV READ_DATA A Note For each read operation the address register should be re specified followed by setting the RD bit high to activate a read cycle even if the target address is consecutive Writing Data to the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A EEPROM_DATA user defined data MOV EED A MOV A 040H set...

Page 42: ...en fast and slow system clock the device has the flexibility to optimize the performance power ratio a feature especially important in power sensitive portable applications Type Name Frequency Pins Internal High Speed RC HIRC 8 12 16MHz Internal Low Speed RC LIRC 32kHz External Low Speed Crystal LXT 32 768kHz XT1 XT2 Oscillator Types System Clock Configurations There are three methods of generatin...

Page 43: ...CC register It is a fully integrated RC oscillator with a typical frequency of 32kHz requiring no external components for its implementation Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage temperature and process variations on the oscillation frequency are minimised Exte...

Page 44: ...al LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 32 768kHz 10pF 10pF Note 1 C1 and C2 values are for guidance only 2 RP 5M 10MΩ is recommended 32 768kHz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes the Quick Start Mode and the Low Power Mode The mode selection is executed using the LXTSP bit in t...

Page 45: ...stem can be configured to obtain maximum application performance The main system clock can come from a high frequency fH or low frequency fSUB source and is selected using the CKS2 CKS0 bits in the SCC register The high speed system clock is sourced from the HIRC oscillator The low speed system clock source can be sourced from the internal clock fSUB If fSUB is selected then it can be sourced by e...

Page 46: ...oming from the HIRC oscillator The high speed oscillator will however first be divided by a ratio ranging from 1 to 64 the actual ratio being selected by the CKS2 CKS0 bits in the SCC register Although a high speed oscillator is used running the microcontroller at a divided clock ratio reduces the operating current SLOW Mode This is also a mode where the microcontroller operates normally although ...

Page 47: ... FSIDEN R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 5 CKS2 CKS0 System clock selection 000 fH 001 fH 2 010 fH 4 011 fH 8 100 fH 16 101 fH 32 110 fH 64 111 fSUB These three bits are used to select which clock is used as the system clock source In addition to the system clock source directly derived from fH or fSUB a divided version of the high speed system oscillator can also be chosen as the...

Page 48: ...en set to 1 after the HIRC oscillator is stable Bit 0 HIRCEN HIRC oscillator enable control 0 Disable 1 Enable LXTC Register Bit 7 6 5 4 3 2 1 0 Name LXTSP LXTF LXTEN R W R W R R W POR 0 0 0 Bit 7 3 Unimplemented read as 0 Bit 2 LXTSP LXT oscillator quick start control 0 Disable Low Power 1 Enable Quick Start This bit is used to control whether the LXT oscillator is operating in the low power or q...

Page 49: ...executed using the CKS2 CKS0 bits in the SCC register while mode switching from the FAST SLOW Mode to the SLEEP IDLE Mode is executed via the HALT instruction When an HALT instruction is executed whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register FAST fSYS fH fH 64 fH on CPU run fSYS on fSUB on SLOW fSYS fSUB f...

Page 50: ...power Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires the selected oscillator to be stable before full mode switching occurs FAST Mode SLOW Mode CKS2 CKS0 111 SLEEP Mode FHIDEN 0 FSIDEN 0...

Page 51: ...DEN 0 FSIDEN 0 HALT instruction is executed IDLE0 Mode FHIDEN 0 FSIDEN 1 HALT instruction is executed IDLE1 Mode FHIDEN 1 FSIDEN 1 HALT instruction is executed IDLE2 Mode FHIDEN 1 FSIDEN 0 HALT instruction is executed Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the HALT instruction in the application program with both the FHIDEN and F...

Page 52: ...hen this instruction is executed under the conditions described above the following will occur The fH and fSUB clocks will be on but the application program will stop at the HALT instruction The Data Memory contents and registers will maintain their present condition The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set and the Watchdog tim...

Page 53: ...gain it will take a considerable time for the original system oscillator to restart stabilise and allow normal operation to resume After the system enters the SLEEP or IDLE Mode it can be woken up from one of various sources listed as follows An external falling edge on Port A A system interrupt A WDT overflow When the device executes the HALT instruction it will enter the SLEEP or IDLE mode and t...

Page 54: ...ut period as well as the enable and reset MCU operation WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 0 1 1 Bit 7 3 WE4 WE0 WDT function control 10101 or 01010 Enable Other values Reset MCU When these bits are changed to any other values due to environmental noise the microcontroller will be reset this reset operation will ...

Page 55: ...d 10101B it will reset the device after a delay time tSRESET After power on these bits will have a value of 01010B WE4 WE0 Bits WDT Function 01010B or 10101B Enable Any other value Reset MCU Watchdog Timer Enable Reset Control Under normal program operation a Watchdog Timer time out will initialise a device reset and set the status bit TO However if the system is in the SLEEP or IDLE Mode when a W...

Page 56: ...imer overflows and resets the microcontroller All types of reset operations result in different register conditions being set Reset Functions There are several ways in which a microcontroller reset can occur through events occurring internally Power on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller As well as ensuring tha...

Page 57: ...WRF WDTC register software reset flag Described elsewhere Low Voltage Reset LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device The LVR function is always enabled in the FAST and SLOW modes with a specific LVR voltage VLVR If the supply voltage of the device drops to within a range of 0 9V VLVR such as might occur when changing the batt...

Page 58: ...fined register values above will also result in the generation of an MCU reset The reset operation will be activated after a delay time tSRESET However in this situation the register contents will be reset to the POR value RSTFC Register Bit 7 6 5 4 3 2 1 0 Name RSTF LVRF LRF WRF R W R W R W R W R W POR 0 x 0 0 x unknown Bit 7 4 Unimplemented read as 0 Bit 3 RSTF RSTC register software reset flag ...

Page 59: ... Conditions The different types of reset described affect the reset flags in different ways These flags known as PDF and TO are located in the status register and are controlled by various microcontroller operations such as the SLEEP or IDLE Mode function or Watchdog Timer The reset flags are shown in the table TO PDF Reset Conditions 0 0 Power on reset u u LVR reset during FAST or SLOW Mode opera...

Page 60: ...0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u MP2H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u RSTFC 0 x 0 0 u 1 u u u u u u u u u u INTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u INTC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u INTC3 0 0 0 0 0 0 0 0 0 0 0 0 u u u u PA 1111 111...

Page 61: ...1 1 1 1 u u u u u u PDC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u PDOM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u PWRDET x 0 u 0 u 0 u u RSTC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 u u u u u u u u TKTMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u TK16DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 62: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM1DH 0 0 0 0 0 0 u u CTM1AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM1AH 0 0 0 0 0 0 u u OVPC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u OVPC1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 u u u u u u u u OVPC2 0 0 0 0 0 0 0 0 0 0 0 0 u u u u OVPD...

Page 63: ...0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 Unimplemented read as 0 I O Logic Function Register List Pull high Resistors Many product applications require pull high resistors for their switch inputs usually r...

Page 64: ...l For the I O pin to function as an input the corresponding bit of the control register must be written as a 1 This will then allow the logic state of the input pin to be directly read by instructions When the corresponding bit of the control register is written as a 0 the I O pin will be set as a CMOS output If the pin is currently set as an output instructions can still be used to read the outpu...

Page 65: ...1 Source current Level 1 10 Source current Level 2 11 Source current Level 3 Max Bit 3 2 SLEDC03 SLEDC02 PA7 PA4 source current selection 00 Source current Level 0 Min 01 Source current Level 1 10 Source current Level 2 11 Source current Level 3 Max Bit 1 0 SLEDC01 SLEDC00 PA3 PA0 source current selection 00 Source current Level 0 Min 01 Source current Level 1 10 Source current Level 2 11 Source c...

Page 66: ...NS4 PCNS3 PCNS2 PCNS1 PCNS0 I O Port Sink Current Selection Register List SLEDCOM0 Register Bit 7 6 5 4 3 2 1 0 Name PANS7 PANS6 PANS5 PANS4 PANS3 PANS2 PANS1 PANS0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 PANS7 PA7 sink current selection 0 Sink current Level 0 Min 1 Sink current Level 1 Max Bit 6 PANS6 PA6 sink current selection 0 Sink current Level 0 Min 1 Sink current Level...

Page 67: ...t 2 PBNS2 PB2 sink current selection 0 Sink current Level 0 Min 1 Sink current Level 1 Max Bit 1 PBNS1 PB1 sink current selection 0 Sink current Level 0 Min 1 Sink current Level 1 Max Bit 0 PBNS0 PB0 sink current selection 0 Sink current Level 0 Min 1 Sink current Level 1 Max SLEDCOM2 Register Bit 7 6 5 4 3 2 1 0 Name PCNS5 PCNS4 PCNS3 PCNS2 PCNS1 PCNS0 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 ...

Page 68: ...d function is properly selected and also deselected For most pin shared functions to select the desired pin shared function the pin shared function should first be correctly selected using the corresponding pin shared control register After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled However a special point must be noted...

Page 69: ...on selection 00 PA1 PTCK 01 SCL 10 OVPI1 11 KEY3 Bit 1 0 PAS01 PAS00 PA0 pin shared function selection 00 PA0 01 RX 10 CTP1 11 OCPVR PAS1 Register Bit 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PAS17 PAS16 PA7 pin shared function selection 00 PA7 CTCK0 PTCK 01 PA7 CTCK0 PTCK 10 PTP 11 XT2 Bit 5 4 PAS15 PAS14 ...

Page 70: ...function selection 00 PB1 CTCK1 01 TX 10 OVPI0 11 KEY2 Bit 1 0 PBS01 PBS00 PB0 pin shared function selection 00 PB0 CTCK0 01 RX 10 OCPI 11 KEY1 PBS1 Register Bit 7 6 5 4 3 2 1 0 Name PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PBS17 PBS16 PB7 pin shared function selection 00 PB7 01 CTP1B 10 AN5 11 OVPCOUT Bit 5 4 PBS15 PBS14 PB6 p...

Page 71: ...CL 11 RX Bit 3 2 PCS03 PCS02 PC1 pin shared function selection 00 PC1 INT 01 PTPB 10 OVPI1 11 KEY12 Bit 1 0 PCS01 PCS00 PC0 pin shared function selection 00 PC0 01 PTP 10 OVPI0 11 KEY11 IFS0 Register Bit 7 6 5 4 3 2 1 0 Name SDAPS1 SDAPS0 SCLPS1 SCLPS0 RXPS1 RXPS0 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 4 SDAPS1 SDAPS0 SDA input source pin selection 00 PB3...

Page 72: ...f the I O logic function The wide range of pin shared structures does not permit all types to be shown M U X VDD Control Bit Data Bit Data Bus Write Control Register Chip Reset Read Control Register Read Data Register Write Data Register System Wake up wake up Select I O pin Weak Pull up Pull high Register Select Q D CK Q D CK Q Q S S PA only Logic Function Input Output Structure Programming Consi...

Page 73: ...ition of any of the Port A pins Single or multiple pins on Port A can be set to have this function High Voltage I O Port The device provides several 10V high voltage input output lines known as PD0 PD5 These high voltage I O ports can convert 5V logic output signals to 10V voltage outputs to directly drive TRIACs relays and buzzers Read Data Register PDn PDn_OE Level Shift VCC2 VDD Level Shift VCC...

Page 74: ...0 5 The PDn truth table is shown as follows PDn_OE PDn_DOUT PDn PDn Mode 0 0 Floating Input mode 0 1 1 0 VSS Output mode Short circuit protection is enabled when PWRRDYF 1 1 1 VCC2 High Voltage I O Registers Overall operation of high voltage I O port is controlled using a series of registers The PD register is the data register The PDC register is used to select the input output type The PDOM regi...

Page 75: ...to or greater than the VDET2 voltage it is not yet determined whether the VCC2 voltage is equal to or greater than the VDET1 voltage then the PWRRDYF read value may be 0 or 1 and therefore in an unknown condition Bit 6 1 Unimplemented read as 0 Bit 0 SFRTC HVIO short flag response time selection 0 64 tLIRC 96 tLIRC 1 32 tLIRC 64 tLIRC Voltage Detector An internal voltage detector circuit is used t...

Page 76: ...nput signal PDn_DIN If the PDn_DOUT has the same value as the PDn_DIN it indicates the high voltage I O is in a normal condition and then the clock counter will be cleared If the comparison result of any high voltage I O pins is different the common clock counter will not be cleared When the comparison result is different and the count value of the clock counter is more than 2 3 the short circuit ...

Page 77: ...ge of features The common features of the different TM types are described here with more detailed information provided in the individual Compact and Periodic TM sections Introduction The device contains several TMs and each individual TM can be categorised as a certain type namely Compact Type TM or Periodic Type TM Although similar in nature the different TM types vary in their feature complexit...

Page 78: ... Pins Each of the TMs irrespective of what type has one input pin with the label xTCKn while the Periodic TM has another input pin with the label PTPI The xTMn input pin xTCKn is essentially a clock source for the xTMn and is selected using the xTnCK2 xTnCK0 bits in the xTMnC0 register This external TM input pin allows an external clock source to drive the internal TM The xTCKn input pin can be ch...

Page 79: ...ow byte only takes place when a write or read operation to its corresponding high byte is executed As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above it is recommended to use the MOV instruction to access the CCRA and CCRP low byte registers named xTMnAL and PTMRPL using the...

Page 80: ...CTnOC CTnM1 CTnM0 CTnIO1 CTnIO0 CTMnAF Interrupt CTMnPF Interrupt CTnPOL CCRA CTnCCLR fSUB CTPnB CTPn Note The CTMn external pins are pin shared with other functions so before using the CTMn function the relevant pin shared function registers must be set properly Compact Type TM Block Diagram n 0 1 Compact Type TM Operation The size of Compact TM is 10 bit wide and its core is a 10 bit count up co...

Page 81: ...unter operation When in a Pause condition the CTMn will remain powered up and continue to consume power The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again Bit 6 4 CTnCK2 CTnCK0 CTMn counter clock selection 000 fSYS 4 001 fSYS 010 fH 16 011 fH 64 100 fSUB 101 fSUB 110 CTCKn rising edge clock...

Page 82: ...00 Compare Match Output Mode 01 Undefined 10 PWM Output Mode 11 Timer Counter Mode These bits set the required operating mode for the CTMn To ensure reliable operation the CTMn should be switched off before any changes are made to the CTnM1 and CTnM0 bits In the Timer Counter Mode the CTMn output pin pin state is undefined Bit 5 4 CTnIO1 CTnIO0 CTMn external pin CTPn function selection Compare Mat...

Page 83: ...if the PWM signal is active high or active low Bit 2 CTnPOL CTMn CTPn output polarity control 0 Non invert 1 Invert This bit controls the polarity of the CTPn output pin When the bit is set high the CTMn output pin will be inverted and not inverted when the bit is zero It has no effect if the CTMn is in the Timer Counter Mode Bit 1 CTnDPX CTMn PWM duty period control 0 CCRP period CCRA duty 1 CCRP...

Page 84: ...g it can be cleared by three methods These are a counter overflow a compare match from Comparator A and a compare match from Comparator P When the CTnCCLR bit is low there are two ways in which the counter can be cleared One is when a compare match from Comparator P the other is when the CCRP bits are all zero which allows the counter to overflow Here both CTMnAF and CTMnPF interrupt request flags...

Page 85: ...its are zero then no pin change will take place Counter Value 0x3FF CCRP CCRA CTnON CTnPAU CTnPOL CCRP Int Flag CTMnPF CCRA Int Flag CTMnAF CTMn O P Pin Time CCRP 0 CCRP 0 Counter overflow CCRP 0 Counter cleared by CCRP value Pause Resume Stop Counter Restart CTnCCLR 0 CTnM 1 0 00 Output pin set to initial Level Low if CTnOC 0 Output Toggle with CTMnAF flag Note CTnIO 1 0 10 Active High Output sel...

Page 86: ...not affected by CTMnAF flag Remains High until reset by CTnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTnPOL is high CTMnPF not generated No CTMnAF flag generated on CCRA overflow Output does not change CTnCCLR 1 CTnM 1 0 00 CCRA Int Flag CTMnAF CCRP Int Flag CTMnPF Compare Match Output Mode CTnCCLR 1 n 0 1 Note 1 With CTnCCLR 1 a Co...

Page 87: ...sed to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CTnDPX bit in the CTMnC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA...

Page 88: ...y Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when CTnPOL 1 PWM Period set by CCRP CTMn O P Pin CTnOC 0 CCRA Int Flag CTMnAF CCRP Int Flag CTMnPF CTnDPX 0 CTnM 1 0 10 PWM Output Mode CTnDXP 0 n 0 1 Note 1 Here CTnDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when CTnIO...

Page 89: ... Counter Reset when CTnON returns high PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when CTnPOL 1 PWM Period set by CCRA CTMn O P Pin CTnOC 0 CTnDPX 1 CTnM 1 0 10 PWM Output Mode CTnDXP 1 n 0 1 Note 1 Here CTnDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when CTnIO 1 0...

Page 90: ...en by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP and CCRA comparators are 10 bit wide whose value is respectively compared with all counter bits The only way of changing the value of the 10 bit counter using the ...

Page 91: ...fH 16 011 fH 64 100 fSUB 101 fSUB 110 PTCK rising edge clock 111 PTCK falling edge clock These three bits are used to select the clock source for the PTM The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the oscillator section Bit 3 PTON PT...

Page 92: ... how the PTM external pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the PTM is running In the Compare Match Output Mode the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a compare match occurs from the Comparator A The PTM output pin can be set to switch high switch low or to toggle its present state ...

Page 93: ...t has no effect if the PTM is in the Timer Counter Mode Bit 1 PTCAPTS PTM capture trigger source selection 0 From PTPI pin 1 From PTCK pin Bit 0 PTCCLR PTM counter clear condition selection 0 Comparator P match 1 Comparator A match This bit is used to select the method which clears the counter Remember that the Periodic TM contains two comparators Comparator A and Comparator P either of which can ...

Page 94: ...R 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 PTM CCRA High Byte Register bit 1 bit 0 PTM 10 bit CCRA bit 9 bit 8 PTMRPL Register Bit 7 6 5 4 3 2 1 0 Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PTRP7 PTRP0 PTM CCRP Low Byte Register bit 7 bit 0 PTM 10 bit CCRP bit 7 bit 0 PTMRPH Register Bit 7 6 5 4 3 2 1 0 Name PTRP9 P...

Page 95: ...e only the PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when PTCCLR is high no PTMPF interrupt request flag will be generated In the Compare Match Output Mode the CCRA cannot be cleared to zero If the CCRA bits are all zero the counter will overflow when it reaches its maximum 10 bit 3FF Hex value however here t...

Page 96: ... Toggle with PTMAF flag Note PTIO 1 0 10 Active High Output select Here PTIO 1 0 11 Toggle Output select Output not affected by PTMAF flag Remains High until reset by PTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTPOL is high PTCCLR 0 PTM 1 0 00 Compare Match Output Mode PTCCLR 0 Note 1 With PTCCLR 0 a Comparator P match will clear t...

Page 97: ...t Here PTIO 1 0 11 Toggle Output select Output not affected by PTMAF flag Remains High until reset by PTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTPOL is high PTMPF not generated No PTMAF flag generated on CCRA overflow Output does not change PTCCLR 1 PTM 1 0 00 Compare Match Output Mode PTCCLR 1 Note 1 With PTCCLR 1 a Comparator A...

Page 98: ...alues As both the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible In the PWM Output Mode the PTCCLR bit has no effect as the PWM period Both of the CCRP and CCRA registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used ...

Page 99: ...TON bit low Counter Reset when PTON returns high PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts When PTPOL 1 PWM Period set by CCRP PTM O P Pin PTOC 0 PTM 1 0 10 PWM Output Mode Note 1 The counter is cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when PTIO 1 0 00 or 01 4 The PT...

Page 100: ...d the pulse leading edge will be generated The PTON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the PTON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the PTON bit and thus ...

Page 101: ...hen PTPOL 1 No CCRP Interrupts generated PTM O P Pin PTOC 0 PTCK pin Software Trigger Cleared by CCRA match PTCK pin Trigger Auto set by PTCK pin Software Trigger Software Clear Software Trigger Software Trigger PTM 1 0 10 PTIO 1 0 11 Single Pulse Output Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the PTCK pin or by setting the PTON bit high 4 A PTCK pin active ...

Page 102: ...generated Irrespective of what events occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a PTM interrupt will also be generated Counting the nu...

Page 103: ...nter Stop PTIO 1 0 Value XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note 1 PTM 1 0 01 and active edge set by the PTIO 1 0 bits 2 A PTM Capture input pin active edge transfers the counter value to CCRA 3 PTCCLR bit not used 4 No output function PTOC and PTPOL bits are not used 5 CCRP determines the counter value...

Page 104: ...voltage VOCPAO into a 12 bit digital value The external or internal analog signal to be converted is determined by the SAINS and SACS bit fields When the external analog signal is to be converted the corresponding external channel input pin function should first be properly configured and then the desired external channel input should be selected using the SAINS and SACS fields Note that when the ...

Page 105: ...contents will be unchanged if the A D converter is disabled ADRFS SADOH SADOL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A D Converter Data Registers A D Converter Control Registers SADC0 SADC1 To control the function and operation of the A D converter two control registers known as SADC0 and SADC1 are provided Th...

Page 106: ...e 1 Enable This bit controls the A D internal function This bit should be set to one to enable the A D converter If the bit is set low then the A D converter will be switched off reducing the device power consumption When the A D converter function is disabled the contents of the A D data register pair known as SADOH and SADOL will be unchanged Bit 4 ADRFS A D conversion data format selection 0 A ...

Page 107: ... D converter power voltage as the reference voltage source When the internal reference voltage source is selected the external VREF pin cannot be configured as the reference voltage input by properly configuring the relevant pin shared control bits Otherwise the external input voltage on the VREF pin will be connected to the internal A D converter power This will result in unpredictable situations...

Page 108: ...gether with the external channel input This will result in unpredictable situations SAINS 2 0 SACS 3 0 Input Signals Description 000 101 11x 0000 0111 AN0 AN7 External channel analog input ANn 1xxx Floating no external channel is selected 001 1xxx VBG Internal Bandgap reference voltage 010 1xxx VCC1O Internal high voltage power VCC1 divided voltage 011 1xxx VCC2O Internal high voltage power VCC2 d...

Page 109: ...sing the ADCEN bit in the SADC0 register This bit must be set high to power on the A D converter When the ADCEN bit is set high to power on the A D converter internal circuitry a certain delay as indicated in the timing diagram must be allowed before an A D conversion is initiated Even if no pins are selected for use as A D inputs by configuring the relevant pin shared control bits if the ADCEN bi...

Page 110: ...erted go to Step 5 Step 4 If the SAINS field is set to select the external channel input the corresponding pin should be configured as an A D input function by selecting the relevant function control bits Then the desired external channel input is selected by configuring the SACS field Then go to Step 6 Step 5 Before the A D input signal is selected to come from the internal analog signal by confi...

Page 111: ... must be taken as if the input voltage is not at a valid logic level then this may lead to some increase in power consumption A D Transfer Function As the device contains a 12 bit A D converter its full scale converted digitised value is equal to FFFH Since the full scale analog input value is equal to the actual A D converter reference voltage VREF this gives a single bit analog input value of re...

Page 112: ...C1 a A D input signal comes from external channel select VREF pin as A D reference voltage source mov a 80h mov PAS0 a set PAS0 to configure pin VREF mov a 02h mov PAS1 a set PAS1 to configure pin AN0 mov a 20h mov SADC0 a enable the A D converter and connect AN0 channel to A D converter start_conversion clr START high pulse on start bit to initiate conversion set START reset A D clr START start A...

Page 113: ..._conversion clr START high pulse on START bit to initiate conversion set START reset A D clr START start A D clr ADF clear ADC interrupt request flag set ADE enable ADC interrupt set EMI enable global interrupt ADC interrupt service routine ADC_ISR mov acc_stack a save ACC to user defined memory mov a STATUS mov status_stack a save STATUS to user defined memory mov a SADOL read low byte conversion...

Page 114: ...Key Module Touch Key 12 Mn n 0 2 M0 KEY1 KEY4 M1 KEY5 KEY8 M2 KEY9 KEY12 Touch Key Structure Touch Key Register Definition Each touch key module which contains four touch key functions has its own suite registers The following table shows the register set for each touch key module The Mn within the register name refers to the Touch Key module number The device has three Touch Key Modules Register ...

Page 115: ...e following equation shown Time slot counter overflow time 256 TKTMR 7 0 32 tTSC where tTSC is the time slot counter clock period TKC0 Register Bit 7 6 5 4 3 2 1 0 Name TKRCOV TKST TKCFOV TK16OV TSCS TK16S1 TK16S0 R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 TKRCOV Touch key time slot counter overflow flag 0 No overflow occurs 1 Overflow occurs This bit can...

Page 116: ... occurs This bit is set high by the touch key function 16 bit counter overflow and must be cleared to 0 by application programs Bit 2 TSCS Touch key time slot counter select 0 Each touch key module uses its own time slot counter 1 All touch key modules use Module 0 time slot counter Bit 1 0 TK16S1 TK16S0 Touch key function 16 bit counter clock source select 00 fSYS 01 fSYS 2 10 fSYS 4 11 fSYS 8 TK...

Page 117: ...le n reference oscillator capacitor value The reference oscillator internal capacitor value TKMnRO 9 0 50pF 1024 TKMnC0 Register Bit 7 6 5 4 3 2 1 0 Name MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2 MnSOF1 MnSOF0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 MnMXS1 MnMXS0 Multiplexer Key Selection Bit Touch Key Module Number MnMXS 1 0 M0 M1 M2 00 KEY1 KEY5 KEY9 01 KEY2 KEY6 KEY10 1...

Page 118: ...gister Bit 7 6 5 4 3 2 1 0 Name MnTSS MnROEN MnKOEN MnK4EN MnK3EN MnK2EN MnK1EN R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 MnTSS Touch key module n time slot counter clock source selection 0 Touch key module n reference oscillator 1 fSYS 4 Bit 6 Unimplemented read as 0 Bit 5 MnROEN Touch key module n Reference oscillator enable control 0 Disable 1 Enable Bit 4 MnKOEN Touch key module ...

Page 119: ... bits Each touch key has its own independent sense oscillator Therefore there are four sense oscillators within each touch key module During this reference clock fixed interval the number of clock cycles generated by the sense oscillator is measured and it is this value that is used to determine if a touch action has been made or not At the end of the fixed reference clock time interval a Touch Ke...

Page 120: ...he keys which are enabled The 16 bit C F counter 16 bit counter 5 bit time slot unit period counter and 8 bit time slot counter in all modules will be automatically cleared More details regarding the touch key interrupt is located in the interrupt section of the datasheet Programming Considerations After the relevant registers are set the touch key detection process is initiated by changing the TK...

Page 121: ...known as a Programmable Gain Amplifier or PGA This PGA can also be configured to operate in the non inverting inverting or input offset calibration mode determined by the OCPEN1 OCPEN0 bits in the OCPC0 register After the current is converted and amplified to a specific voltage level it will be compared with a reference voltage provided by an 8 bit D A converter The 8 bit D A converter reference v...

Page 122: ... OCPC1 G2 G1 G0 OCPDEB2 OCPDEB1 OCPDEB0 OCPDA D7 D6 D5 D4 D3 D2 D1 D0 OCPOCAL OCPOOFM OCPORSP OCPOOF5 OCPOOF4 OCPOOF3 OCPOOF2 OCPOOF1 OCPOOF0 OCPCCAL OCPCOUT OCPCOFM OCPCRSP OCPCOF4 OCPCOF3 OCPCOF2 OCPCOF1 OCPCOF0 OCP Register List OCPC0 Register Bit 7 6 5 4 3 2 1 0 Name OCPEN1 OCPEN0 OCPVRS OCPCHY OCPO R W R W R W R W R W R POR 0 0 0 0 0 Bit 7 6 OCPEN1 OCPEN0 OCP function operating mode selection...

Page 123: ...110 63 64 tDEB 111 127 128 tDEB Note tDEB 1 fSYS OCPDA Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 OCP D A converter output voltage control bits DAC VOUT D A converter reference voltage 256 OCPDA 7 0 OCPOCAL Register Bit 7 6 5 4 3 2 1 0 Name OCPOOFM OCPORSP OCPOOF5 OCPOOF4 OCPOOF3 OCPOOF2 OCPOOF1 OCPOOF0 R W R W R ...

Page 124: ... Offset Calibration Mode disabled 1 Input Offset Calibration Mode enabled This bit is used to control the OCP comparator input offset Calibration function The OCPEN1 and OCPEN0 bits must first be set to 11 and then the OCPCOFM bit must be set to 1 followed by the OCPOOFM bit being setting to 0 then the comparator input offset calibration mode will be enabled Refer to the Comparator Input Offset Ca...

Page 125: ...the OCPOOF 5 0 value by 1 and then read the OCPCOUT bit If the OCPCOUT bit state has not changed then repeat Step 5 until the OCPCOUT bit state has changed If the OCPCOUT bit state has changed record the OCPOOF value as VOOS2 and then go to Step 6 Step5 Restore the operational amplifier input offset calibration value VOOS into the OCPOOF 5 0 bit field The offset Calibration procedure is now finish...

Page 126: ... Voltage Protection Operation The OVP circuit is used to prevent the input voltage from being in an unexpected level range The voltage can be sourced from the OVPI0 or OVPI1 pin which is determined by the OVPS1 OVPS0 bits in the OVPC2 register The selected OVP input voltage is compare with a reference voltage provided by an 8 bit D A converter The 8 bit D A converter reference input signal is supp...

Page 127: ... 6 5 4 3 2 1 0 Name OVPO OVPSPOL OVPEN OVPDEB2 OVPDEB1 OVPDEB0 R W R R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 OVPO OVP comparator output bit after debounce 0 Positive input voltage negative input voltage 1 Positive input voltage negative input voltage Bit 6 OVPSPOL OVP debounced output signal polarity control 0 Non invert 1 Invert This bit will determine the OVP interrupt occurrence condition whe...

Page 128: ...e comparator input offset cancellation operation and the value for the OVP comparator input offset cancellation can be restored into this bit field More detailed information is described in the Comparator Input Offset Cancellation section OVPC2 Register Bit 7 6 5 4 3 2 1 0 Name HYS1 HYS0 OVPS1 OVPS0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 HYS1 HYS0 OVP comparator hy...

Page 129: ...nal peripheral devices such as sensors EEPROM memory etc Originally developed by Philips it is a two line low speed serial interface for synchronous serial data transfer The advantage of only two lines for communication relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications Devic...

Page 130: ...k Diagram START signal from Master Send slave address and R W bit from Master Acknowledge from slave Send data byte from Master Acknowledge from slave STOP signal from Master I2 C Interface Operation The IICDEB1 and IICDEB0 bits determine the debounce time of the I2 C interface This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches...

Page 131: ...tes data to the I2 C bus the actual data to be transmitted must be placed in the IICD register After the data is received from the I2 C bus the device can read it from the IICD register Any transmission or reception of data from the I2 C bus must be made via the IICD register IICD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x un...

Page 132: ... the SDA and SCL lines will lose their I2 C function and the I2 C operating current will be reduced to a minimum value When the bit is high the I2 C interface is enabled The I2 C configuration option must have first enabled the I2 C interface for this bit to be effective If the IICEN bit changes from low to high the contents of the I2 C control bits such as HTX and TXAK will remain at the previous...

Page 133: ...p control 0 Disable 1 Enable This bit should be set to 1 to enable the I2 C address match wake up from the SLEEP or IDLE Mode If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2 C address match wake up then this bit must be cleared by the application program after wake up to ensure correction device operation Bit 0 RXAK I2 C Bus Receive acknowledge flag 0 S...

Page 134: ...us Start Signal The START signal can only be generated by the master device connected to the I2 C bus and not by the slave device This START signal will be detected by all devices connected to the I2 C bus When detected this indicates that the I2 C bus is busy and therefore the HBB bit will be set A START condition occurs when a high to low transition on the SDA line takes place when the SCL line ...

Page 135: ...ing address If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication When the HAAS flag is high the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver If the SRW flag is high the slave device should be set to be a transmitter so the HTX bit in the IICC1 r...

Page 136: ...m Note When a slave address is matched the device must be placed in either the transmit mode and then write data to the IICD register or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line Start IICTOF 1 SET IICTOEN CLR IICTOF RETI HAAS 1 HTX 1 SRW 1 Read from IICD to release SCL Line RETI RXAK 1 Write data to IICD to release SCL Line CLR HTX CLR...

Page 137: ...egative transition I2 C Time out When an I2 C time out counter overflow occurs the counter will stop and the IICTOEN bit will be cleared to zero and the IICTOF bit will be set high to indicate that a time out condition has occurred The time out condition will also generate an interrupt which uses the I2 C interrupt vector When an I2 C time out occurs the I2 C internal circuitry will be reset and t...

Page 138: ...sses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates The integrated UART function contains the following features Full duplex asynchronous communication 8 or 9 bits character length Even odd or no parity options One or two stop bits Baud rate generator with 8 bit prescaler Parity framing noise and overrun error detection Support fo...

Page 139: ... Rate Generator Only the TXR_RXR register is mapped onto the MCU Data Memory the Transmit Shift Register is not mapped and is therefore inaccessible to the application program Data to be received by the UART is accepted on the external RX pin from where it is shifted in LSB first to the Receiver Shift Register at a rate controlled by the Baud Rate Generator When the shift register is full the data...

Page 140: ...ollowed by an access to the TXR_RXR data register Bit 5 FERR Framing error flag 0 No framing error is detected 1 Framing error is detected The FERR flag is the framing error flag When this read only flag is 0 it indicates that there is no framing error When the flag is 1 it indicates that a framing error has been detected for the current character The flag can also be cleared by a software sequenc...

Page 141: ...cter is not transferred to the transmit shift register 1 Character has transferred to the transmit shift register TXR_RXR data register is empty The TXIF flag is the transmit data register empty flag When this read only flag is 0 it indicates that the character is not transferred to the transmitter shift register When the flag is 1 it indicates that the transmitter shift register has received a ch...

Page 142: ...lection bit When this bit is equal to 1 odd parity type will be selected If the bit is equal to 0 then even parity type will be selected Bit 3 STOPS Number of Stop bits selection 0 One stop bit format is used 1 Two stop bits format is used This bit determines if one or two stop bits are to be used When this bit is equal to 1 two stop bits are used If this bit is equal to 0 then only one stop bit i...

Page 143: ...oating state If the RXEN bit is equal to 1 and the UARTEN bit is also equal to 1 the receiver will be enabled and the RX pin will be controlled by the UART Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver If this situation occurs the RX pin will be in a floating state Bit 5 BRGH Baud Rate speed selection 0 Low speed baud rate 1 High s...

Page 144: ...le interrupt If this bit is equal to 1 and when the transmitter idle flag TIDLE is set due to a transmitter idle condition the UART interrupt request flag will be set If this bit is equal to 0 the UART interrupt request flag will not be influenced by the condition of the TIDLE flag Bit 0 TEIE Transmitter Empty interrupt enable control 0 Transmitter empty interrupt is disabled 1 Transmitter empty i...

Page 145: ...N fH BR 64 1 Giving a value for N 4000000 4800 64 1 12 0208 To obtain the closest value a decimal value of 12 should be placed into the BRG register This gives an actual or calculated baud rate value of BR 4000000 64 12 1 4808 Therefore the error is equal to 4808 4800 4800 0 16 UART Setup and Control For data transfer the UART function utilizes a non return to zero more commonly known as NRZ forma...

Page 146: ...nsmitter There is only one stop bit for the receiver Start Bit Data Bits Address Bit Parity Bit Stop Bit Example of 8 bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9 bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8 bit and 9 bit data formats Bit 0 8 bit Data Format Bit 1 Stop Bit Ne...

Page 147: ...o the TXR_RXR register Clearing the TXIF flag is always achieved using the following software sequence 1 A USR register access 2 A TXR_RXR register write execution The read only TXIF flag is set by the UART hardware and if set indicates that the TXR_RXR register is empty and that other data can now be written into the TXR_RXR register without overwriting the previous data If the TEIE bit is set th...

Page 148: ...ram must ensure that the data is read from TXR_RXR before the third byte has been completely shifted in otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated The steps to initiate a data transfer can be summarized as follows Make the correct selection of BNO PRT and PREN bits to define the word length parity type Configure the BRG register to select t...

Page 149: ...nsferred from the Receive Shift Register RSR to the Receive Data Register TXR_RXR An overrun error can also generate an interrupt if RIE 1 Managing Receiver Errors Several types of reception errors can occur within the UART module the following section describes the various types and how they are managed by the UART Overrun Error OERR The TXR_RXR register is composed of a two byte deep FIFO data b...

Page 150: ...ll jump to its corresponding interrupt vector where it can be serviced before returning to the main program Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set The two transmitter interrupt conditions have their own corresponding enable control bits while the two receiver ...

Page 151: ...e generated every time the last bit of the received word is set If the ADDEN bit is not enabled then a Receiver Data Available interrupt will be generated each time the RXIF flag is set irrespective of the data last bit status The address detect mode and parity enable are mutually exclusive functions Therefore if the address detect mode is enabled then to ensure correct operation the parity functi...

Page 152: ...ally useful in battery applications where the supply voltage will gradually reduce as the battery ages as it allows an early warning battery low signal to be generated The Low Voltage Detector also has the capability of generating an interrupt signal LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC Three bits in this register VLVD2 VLVD0 are u...

Page 153: ...ctor a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions VDD LVDEN LVDO VLVD tLVDS LVD Operation The Low Voltage Detector also has its own interrupt providing an alternative means of low voltage detection in addit...

Page 154: ...se Data Memory as shown in the accompanying table The number of registers depends upon the device chosen but fall into three categories The first is the INTC0 INTC3 registers which configure the primary interrupts The second is the MFI0 MFI1 registers which configure the Multi function interrupts Finally there is an INTEG register to configure the external interrupt trigger edge type Each register...

Page 155: ...TS0 Interrupt edge control for INT pin 00 Disable 01 Rising edge 10 Falling edge 11 Rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 0 Name TBF TKMF INTF TBE TKME INTE EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 TBF Time Base interrupt request flag 0 No request 1 Interrupt request Bit 5 TKMF Touch Key Module interrupt request flag 0 No request...

Page 156: ...T transfer interrupt control 0 Disable 1 Enable Bit 2 IICE I2 C interrupt control 0 Disable 1 Enable Bit 1 MF1E Multi function 1 interrupt control 0 Disable 1 Enable Bit 0 MF0E Multi function 0 interrupt control 0 Disable 1 Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Name OVPF DEF ADF LVF OVPE DEE ADE LVE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 OVPF Over Voltage Protection inte...

Page 157: ...Bit 3 2 Unimplemented read as 0 Bit 1 HVSCE High Voltage Short Circuit interrupt control 0 Disable 1 Enable Bit 0 OCPE Over Circuit Protection interrupt control 0 Disable 1 Enable MFI0 Register Bit 7 6 5 4 3 2 1 0 Name PTMAF PTMPF CTM0AF CTM0PF PTMAE PTMPE CTM0AE CTM0PE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 PTMAF PTM Comparator A match interrupt request flag 0 No request 1 ...

Page 158: ... set high then the program will jump to its relevant vector if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector The global interrupt enable bit if cleared to zero will disable all interrupts When an interrupt is generated the Program Counter which stores the address of the...

Page 159: ...INTE EMI 20H EMI EMI 08H Touch Key Module TKMF TKME EMI 0CH Time Base TBF TBE 10H EMI 14H Multi Function 1 MF1F MF1E EMI 18H 1CH EMI 24H EMI EMI EMI 28H 2CH EMI 30H EMI HVSC HVSCF HVSCE 34H xxE Enable Bits xxF Request Flag auto reset in ISR Legend xxF Request Flag no auto reset in ISR Interrupts contained within Multi Function Interrupts CTM0 Comp A CTM0AF CTM0AE Interrupt Name Request Flags Enabl...

Page 160: ...the Touch Key time slot counter overflow occurs a subroutine call to the relevant interrupt vector will take place When the interrupt is serviced the Touch Key interrupt request flag will be automatically reset and the EMI bit will also be automatically cleared to disable other interrupts Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of a...

Page 161: ...tion interrupt flag will be set when any of its included functions generate an interrupt request flag To allow the program to branch to its respective interrupt vector address when the Multi function interrupt is enabled and the stack is not full and one of the interrupts contained within the Multi function interrupt occurs a subroutine call to the Multi function interrupt vector will take place W...

Page 162: ... detects a low power supply voltage To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and Low Voltage Interrupt enable bit LVE must first be set When the interrupt is enabled the stack is not full and a low voltage condition occurs a subroutine call to the relevant interrupt vector will take place When the Low Voltage Interrupt is service...

Page 163: ...ccurs when a short circuit situation occurs on any one of the high voltage I O pins To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and High Voltage Short Circuit Interrupt enable bit HVSCE must first be set When the interrupt is enabled the stack is not full and an short circuit condition is detected a subroutine call to the High Volta...

Page 164: ...not well controlled the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode the wake up being generated when the interrupt request flag changes from low to high If it is required to prevent a certain interrupt from waking up the microcontroll...

Page 165: ...cation Circuits VSS VCC Touch Key KEY1 Touch Key KEY2 0 1μF Touch Key KEY12 VCC1 VCC2 VCC PD0 Load VDD 16V 100μF 0 1μF 10μF OSC Circuit XT1 XT2 VCC PD1 Load VCC PD5 Load ANn VDD NTC UART Pins I2 C Pins I O COM1 COM2 COM3 COM4 E D C G B F A DISP1 H ACN ACL ACN ACL ACN ACL 0 1μF 16V 100μF R ...

Page 166: ... cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one...

Page 167: ...branch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the conditio...

Page 168: ...CC with Carry result in Data Memory 1Note Z C AC OV SC CZ DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data...

Page 169: ...RET A x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None ITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 2Note None ITABRDL m Increment table pointer TBLP first and ...

Page 170: ... Decimal adjust ACC for Addition with result in Data Memory 2Note C Logic Operation LAND A m Logical AND Data Memory to ACC 2 Z LOR A m Logical OR Data Memory to ACC 2 Z LXOR A m Logical XOR Data Memory to ACC 2 Z LANDM A m Logical AND ACC to Data Memory 2Note Z LORM A m Logical OR ACC to Data Memory 2Note Z LXORM A m Logical XOR ACC to Data Memory 2Note Z LCPL m Complement Data Memory 2Note Z LCP...

Page 171: ... with result in ACC 2Note None Table Read LTABRD m Read table to TBLH and Data Memory 3Note None LTABRDL m Read table last page to TBLH and Data Memory 3Note None LITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None LITABRDL m Increment table pointer TBLP first and Read table last page to TBLH and Data Memory 3Note None Miscellaneous LCLR m Clear Data Memo...

Page 172: ...ccumulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C SC ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC AND A m Logical AND Data Memory to ACC Descr...

Page 173: ...hich previously contained a 1 are changed to 0 and vice versa Operation m m Affected flag s Z CPLA m Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented 1 s complement Bits which previously contained a 1 are changed to 0 and vice versa The complemented result is stored in the Accumulator and the contents of the Data Memory remain un...

Page 174: ...1 Operation m m 1 Affected flag s Z INCA m Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1 The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC m 1 Affected flag s Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address Program...

Page 175: ...ted flag s Z RET Return from subroutine Description The Program Counter is restored from the stack Program execution continues at the restored address Operation Program Counter Stack Affected flag s None RET A x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data Program execut...

Page 176: ...t Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 C C m 7 Affected flag s C RR m Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7 Operation m i...

Page 177: ... ACC ACC m C Affected flag s OV Z AC C SC CZ SBCM A m Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Data Memory Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is po...

Page 178: ...truction while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m 1 Skip if ACC 0 Affected flag s None SNZ m i Skip if Data Memory is not 0 Description If the specified Data Memory is not 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next in...

Page 179: ...ta Memory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is ...

Page 180: ...ed to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None ITABRDL m Increment table pointer low byte first and read table last page to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to...

Page 181: ...is stored in the Accumulator Operation ACC ACC m Affected flag s OV Z AC C SC LADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC LAND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory pe...

Page 182: ...ed If the high nibble is greater than 9 or if the C flag is set then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by adding 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addit...

Page 183: ...Memory are rotated left by 1 bit with bit 7 rotated into bit 0 Operation m i 1 m i i 0 6 m 0 m 7 Affected flag s None LRLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i...

Page 184: ...Data Memory and the carry flag are rotated right by 1 bit Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 C C m 0 Affected flag s C LSBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memor...

Page 185: ...n Bit i of the specified Data Memory is set to 1 Operation m i 1 Affected flag s None LSIZ m Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result...

Page 186: ...ll be set to 1 Operation m ACC m Affected flag s OV Z AC C SC CZ LSWAP m Swap nibbles of Data Memory Description The low order and high order nibbles of the specified Data Memory are interchanged Operation m 3 m 0 m 7 m 4 Affected flag s None LSWAPA m Swap nibbles of Data Memory with result in ACC Description The low order and high order nibbles of the specified Data Memory are interchanged The re...

Page 187: ... Affected flag s None LITABRD m Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the program code addressed by the table pointer TBHP and TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None LITABRDL m...

Page 188: ...gular intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of Packing Ma...

Page 189: ...Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 504 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 31 0 51 C 12 80 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 190: ...Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 705 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 31 0 51 C 17 90 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 191: ... Min Nom Max A 0 472 BSC B 0 394 BSC C 0 472 BSC D 0 394 BSC E 0 032 BSC F 0 012 0 015 0 018 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 12 00 BSC B 10 00 BSC C 12 00 BSC D 10 00 BSC E 0 80 BSC F 0 30 0 37 0 45 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 192: ... are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek ...

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