Hioki BT4560, Instruction Manual, Page: 12 / 62

9

Standard Event Status Enable Register (SESER)
Setting any bit of the Standard Event Status Enable Register to 1 enables access to the corresponding bit of the
Standard Event Status Register.
Standard Event Status Register (SESR) and Standard Event Status Enable Register (SESER)
Status Byte Register (STB)
bit6 bit5 bit4
MSS ESB MAV
Standard Event Status Register (SESR)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Logical sum
← & & & & & & & &
↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
Standard Event Status Enable Register (SESER)

Device-Specific Event Status Registers (ESR0 and ESR1)
This instrument provides two Event Status Registers for controlling events. Each event register is an 8-bit register.
When any bit in one of these Event Status Registers enabled by its corresponding Event Status Enable Register is
set to 1, the following happens:
• For Event Status Register 0, bit 0 (ESB0) of the Status Byte Register (STB) is set to 1.
• For Event Status Register 1, bit 1 (ESB1) of the Status Byte Register (STB) is set to 1.
Event Status Registers 0 and 1 are cleared in the following situations:
• When a
* CLS command is executed
• When an Event Status Register query (
:ESR0?
or
:ESR1?
) is executed
• When the instrument is powered on