Grundig GDV 130, Service Manual

Page: 22 / 36

2 - 5 GRUNDIG Service
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams GDV 130…
Name Number I/O Definition
VCC
LA[21:0]
1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92,
99, 104, 111,
121, 130, 139, 148, 157, 164, 172, 183,
193, 201
23:19,16:10,7:2,207:204
I
O
3.65 V ± 150 mV.
Device address output.
VSS
RESET#
TDMDX
RSEL
8,17,26,34,43,52,60,67,76,84,91,98,103,1
12,120,129,1
38,147,156,163,171,177,184,192,200,208
24
I
I
25
O
I
Ground.
Reset input, active low.
TDM transmit data
ROM Select
RSEL Selection
0 16-bit ROM
1 8-bit ROM
TDMDR
TDMCLK
TDMFS
TDMTSC# 28
29 I
I
30
31 I
O
TWS
SEL_PLL1
TSD
SEL_PLL0
SEL_PLL2
MCLK
32
33
O
I
O
I
36
39 I/O
TDM receive data.
TDM clock input.
TDM frame synch.
TDM output enable, active low.
Audio transmit frame sync.
Select PLL1.
Audio transmit serial data port.
Select PLL0.
SEL_PLL2 SEL_PLL0 Clock Output
0 0 2.5 x DCLK
0 1 3 x DCLK
1 0 3.5 x DCLK
1 1 4 x DCLK
Select PLL2. See the table for pin number 33.
Audio master clock for audio DAC.
TBCK
SDIF_DOBM
RSD
RWS
40
41
I/O
O
45
46
I
I
RBCK
APLLCAP
XIN
XOUT
47
48 I
I
49
50
I
O
Audio transmit bit clock.
S/PDIF (IEC958)Format Output.
Audio receive serial data.
Audio receive frame synch.
Audio receive bit clock.
Analog PLL Capacitor.
Crystal input.
Crystal output.
DMA[11:0]
DCAS#
DOE#
DSCK_EN
DWE#
66:61, 58:53
69 O
O
70
71
O
I
O
DRAS[2:0]#
DB[15:0]
DCS[1:0]#
DQM
74:72
96:93, 90:85, 82:77
O
I/O
97, 100
101 O
O
DRAM address bus.
Column address strobe, active low.
Output enable, active low.
Clock enable, active low.
DRAM write enable, active low.
Row address strobe, active low.
DRAM data bus.
SDRAM chip select [1:0], active low.
Data input / output mask.
DSCK
DCLK
YUV[7:0]
PCLK2XSC
N
102
105 O
I
115:113, 110:106
116
O
I/O
PCLKQSCN
VSYNCH#
HSYNCH#
117
118 I/O
I/O
119 I/O
Clock to SDRAM.
Clock Input(27MHz).
8-bit YUV output.
2X pixel clock.
Pixel clock.
Vertical synch for screen video interface,
programmable for rising or falling edge, active
low.
Horizontal synch for screen video interface,
programmable for rising or falling edge, active
low.
HD[15:0]
HCS1FX#
HCS3FX#
HIOCS16#
141:140, 137:131, 128:122
152 O
O
153
151 O
I
HA[2:0]
VPP
HWR#/
DCI_ACK#
HRD#DCI_C
LK
158, 155:154
159
I/O
I
149
150
I,I
I,I
Host data bus
Host select 1.
Host select 3.
Device 16-bit data transfer.
Host address bus.
Peripheral protection voltage.
Host write/DCI Interface Acknowledge Signal,
active low.
Host read/DCI Interface Clock.
HD[15:0]
HWRQ#
HRDQ#
HIRQ
141:140, 137:131, 128:122
142 I/O
O
143
144 O
I/O
HRST#
HIORDY
HWR#
AUX[7:0]
145
146
O
I
149
169:165, 162:160
O
I/O
Host data bus.
Host write request.
Host read request.
Host interrupt.
Host reset.
Host I/O ready
Host write request.
Auxiliary ports.
LOE#
LCS[3:0]#
LD[15:0]
LWRLL#
170
176:173 O
O
197:194, 191:185, 182:178
198 I/O
O
LWRHL#
NC
199
37, 38, 42, 203:202
O
Device output enable, active low.
Chip select[3:0], active low.
Device data bus.
Device write enable, active low.
Device write enable, active low.
No Connect pins. Leave open