GRUNDIG Service
2 - 4
GDV 130…
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
LCS1#
LOE#
LD0
VSS
LCS3#
LCS2#
AUX0
LA
21
LA
20
RE
S
E
T
#
VC
C
HI
O
C
S
1
6
#
HA
1
VSS
HA
0
HW
R
#/DCI_CLK
HR
D
#/DC_A
CK#
H
D
4
/DCI
4
H
D
5
/DCI
5
H
D
6
/DCI
6
H
D
2
/DCI
2
H
D
3
/DCI
3
VC
C
VCC
DB8
VC
C
DB5
DB9
DCS0#
VC
C
VS
S
TS
D
/S
E
L
_
P
L
L
0
SE
L
_
P
L
L
2
TD
M
F
S
TD
M
C
L
K
TD
M
D
R
TD
M
T
S
C
#
TW
S
/S
E
L
_
P
L
L
1
VC
C
LA
4
LA
5
LA
6
LA
7
LA
8
LA
9
VS
S
VC
C
LA
10
LA
11
LA
12
LA
13
LA
14
LA
15
LA
16
VS
S
VC
C
LA
17
LA
18
LA
19
T
D
MD
X/
R
S
EL
VS
S
SPD
IF
_
D
O
BM
NC
VS
S
MC
L
K
TB
C
K
VCC
VCC
VS
S
VSS
DQM
RS
D
RW
S
RB
C
K
APL
L
C
AP
XI
N
XO
U
T
VC
C
DSCK
VSS
DB15
DB13
DB11
DB1
VSS
DRAS2#
DRAS0#
DOE#/DSCK_EN
VCC
DMA9
DMA7
VSS
DMA5
DMA3
VCC
DCS1#
DB14
DB12
DB10
DB0
VCC
DRAS1#
DWE#
DCAS#
VSS
DMA8
DMA6
VCC
DMA4
DMA2
VSS
DB7
DB6
VSS
DB4
DB3
DB2
DMA11
DMA10
DMA1
DMA0
HC
S
3
F
X
#
HC
S
1
F
X
#
VSS
HI
O
R
D
Y
VSS
HD
13
HD
12
HD
11
HD
10
HD
9
H
D
8
/DCI
_F
D
S
#
VSS
H
IRQ
/D
C
I_
E
RR#
HR
S
T
#
HR
D
Q
#
HW
R
Q
#
D
C
I_R
E
Q
#
HD
15
HD
14
VC
C
H
D
7
/DCI
7
H
D
1
/DCI
1
H
D
0
/DCI
0
VC
C
VSS
HS
Y
N
C
H
#
PC
L
K
2
XSC
N
YU
V7
YU
V6
PC
L
K
Q
S
C
N
VSY
N
C
H
#
YU
V5
VSS
VC
C
YU
V4
YU
V3
YU
V2
YU
V1
YU
V0
DC
LK
VC
C
AUX7
AUX6
VCC
LD1
LD2
LA3
LD12
VCC
HA2
VPP
VCC
LD3
LD5
LD9
LD13
LWRHL#
NC
AUX1
AUX3
LD4
LD6
LD10
LD14
VSS
LA0
AUX2
AUX4
VCC
LD7
LD11
LD15
VCC
LA1
VSS
AUX5
VSS
LD8
VSS
LWRLL#
NC
LA2
VSS
VCC
LCS0#
VSS
Host/DCI Interface
Video
Audio
Memory
RISC processor Interface
auxiliary
208-Pin
PQFP Package
Swan-2
TM
ES4318
NC
NC
Figure 3 Swanª ES4318 Block Diagram
AUX[7:0]
HSYNC#
PCLK2XSCN
PCLKQSCN
RESET#
VSYNC#
XIN
XOUT
Miscellaneous
Huffman
Decoder
On Screen
Video
Video Output
Processor
32-Bit
Host
Serial Audio
Processor
Display
Interface
Interface
Serial
Audio
Interface
TDM
Interface
DRAM
Screen
Display
Misc.
Processor
Interface
Host
Interface
RSEL
YUV[7:0]
RISC
DRAM
Interface
LOE#
LA[21:0]
LD[15:0]
LCS#[3:0]
LWRHL#
LWRLL#
HIORDY
HCS[1,3]FX#
HA[2:0]
HIOCS16#
HWR#
HD[15:0]
HRDQ#
HWRQ#
HIRQ#
HRST#
RSD
RWS
RBCK
SPDIF_DOBM
TBCK
MCLK
TSD
TWS
TDMCLK
TDMDR
TDMDX
TDMFS
TDMTSC#
SEL_PLL [2:0]
DSCK_EN
DQM
DCS#[1:0]
DMA[11:0]
DWE#
DOE#
DRAS#[2:0]
DB[I5:0]
APLLCAP
Registers
DCAS#
DSCK
HRD#
TDM
Interface
System
DVD
Descramble
2Kx32 ROM
512x32 SRAM
DCI
Interface
DCI
Interface
DCI5
DCI1
DCI_ACK#
DCI2
DCI4
DCI_CLK
DCI_REQ#
DCI_ERR#
DCI_FDS#
DCI7
DCI6
DCI3
DCI0
DMA
Controller
Demultiplexer
Sub-Picture
Decoder
IC U101 (ES 4318)
