GRUNDIG Service
2 - 15
k
GDV 100 D
Descriptions
7101
6
1
17
7
8
9
11
12
13
14
15
4
5
16
19
3
2
20
10
18
PCF8584
PARALLEL BUS CONTROL
FILTER
DIGITAL
FILTER
DIGITAL
CONTROL
SCL
CONTROL
DATA
SDA
SCL
AND READ BUFFER
DATA SHIFT REGISTER S0
SHIFT REGISTER
MSB
REGISTERS
READ BUFFER
DB7
DB4
DB3
IACKN
DB2
DB1
CLK
DB0
VSS
VDD
DB5
DB6
INTN
RDN
WRN
A0
CSN
RESN
ARBITR LOGIC
BUS BUSY LOG
SCL MULTIPL
CLOCK PRESC
RES/STR CON
INTERR CON
BUS BUF CON
REG ACC CON
Pin
Name
I/O
Function
1
CLK
I
clock input from microcontroller clock generator
2
SDA
I/O
I
2
C-bus serial data input/output
3
SCL
I/O
I
2
C-bus serial clock input/output
4
IACKN
I
interrupt acknowledge input
5
INTN
O
interrupt output
6
A0
I
register select input
7-9,
11-15
DB[0:7]
I/O
bi-directional 8-bit bus
10
VSS
-
ground
16
DTACKN
O
data transfer control output
17
CSN
I
chip select input
18
RWN
I
write control input
19
RESN
I
reset input
20
VDD
-
supply voltage
IC7101
PCF8584: I
2
C-bus controller
Function Overview
The PCF8584 is an integrated circuit designed in CMOS technology
which serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I
2
C-bus. The PCF8584
provides both master and slave functions.
Communication with the I
2
C-bus is carried out on a byte-wise basis
using interrupt or polled handshake. It controls all the I
2
C-bus specific
sequences, protocol, arbitration and timing. The PCF8584 allows
parallel-bus systems to communicate bi-directionally with the I
2
C-bus.
IC7102, IC7103, IC7200, IC7302, IC7304…IC7306
µ
PD424260A: DRAM
Function Overview
Fast-page dynamic RAM organized as 262,144 words by 16 bits and
designed to operate from a single power supply. Used as DRAM
memory for the CPU (IC7102 and IC7103), as DRAM (IC7200) for the
DVD Stream Manager and as DRAM (IC7302, IC7304, IC7305,
IC7306) for MPEG decoder L64005.
IC7104, IC7105
29F800: Flash memory
Function Overview
The first generation DVD players have the application software in
FLASH memory ICs. These are only used in the first few months of
production to allow later updating. The later generation of DVD Players
has the software stored in ROMs.
– Device:
AM29F800
– Memory organization: 512K x 16/ 1M x 8
– Speed:
70ns
– Sectors:
Boot
– Package:
44-SOIC / 48-TSOP
IC7106, IC7107
EPROM memory
EPROM (S) will contain application software, will be replaced by ROM.
IC7109
MK2742: Clock synthesizer
Function Overview
The MK2742 is a clock synthesizer for MPEG1, MPEG2 and set-top
box based applications. Using analog Phase-Locked Loop (PLL)
techniques, the device accepts a 27MHz crystal or clock input to
produce multiple output clocks including the processor clock, 27MHz,
13.5MHz, 3.6864MHz, and a selectable audio clock. The audio clocks
and the 13.5MHz, 27MHz, and 3.68MHz clocks are exactly frequency
locked to the 27MHz input with zero ppm error, allowing audio and
video to track exactly.
10
9
14
6
8
12
5
11
7
15
16
1
4
13
3
2
PS0
AS0
7109
MK2742
PS1
PS2
X2
X1
AS1
CLOCK
BUFFER/
CRYSTAL
OSCILL.
CLOCK SYNTHESIS AND
CONTROL CICUITRY
CLOCK SYNTHESIS
AND
CONTROL CICUITRY
GND1
VDD1
CLOCK
SYNTHESIS
+2
GND2
VDD2
OUTPUT
BUFFER
OUTPUT
BUFFER
OUTPUT
BUFFER
OUTPUT
OUTPUT
BUFFER
BUFFER
PCLK
ACLK
27M
3_68M
13_5M
Pin
Name
I/O
Function
1
PS2
I
processor clock select 2
2
X2
O
crystal connection
3
X1
I
crystal connection
4
VDD
-
connect to +5V
5
GND
-
connect to ground
6
ACLK
O
audio clock output
7
PCLK
O
processor clock output
8
AS0
I
audio clock select 0
9
27M
O
27.00MHz clock output
10
13.5M
O
13.5MHz clock output
11
GND
-
connect to ground
12
AS1
I
audio clock select 1
13
VDD
-
connect to +5V
14
3.68M
O
3.6864MHz clock output
15
PS0
I
processor clock select 0
16
PS1
I
processor clock select 1
Pin name
Function
A[0:8]
Address inputs
D[0:15]
Data inputs and outputs
LCASN,
UCASN
Column address strobes
OEN
Output enable
RASN
Row address strobe
WEN
Write enable
GND
Ground
VCC
+5V
NC
No connection
