3 Development Board Circuit
3.9 LVDS
DBUG405-1.0E
20(25)
3.9.3
Pinout
Table 3-11 J3 FPGA Pinout
Signal Name
Pin No.
Socket Pin No.
BANK
Description
I/O
F_LVDS_A1_P 140
1
0
A Channel 1+
3.3V
F_LVDS_A1_N 139
2
0
A Channel 1-
3.3V
GND
-
3
-
-
-
GND
-
4
-
-
-
F_LVDS_A2_P 138
5
0
A Channel 2+
3.3V
F_LVDS_A2_N 137
6
0
A Channel 2–
3.3V
GND
-
7
-
-
GND
-
8
-
-
F_LVDS_A3_P 134
9
0
A Channel 3+
3.3V
F_LVDS_A3_N 133
10
0
A Channel 3–
3.3V
GND
-
11
-
-
GND
-
12
-
-
F_LVDS_A4_P 132
13
0
A Channel 4+
3.3V
F_LVDS_A4_N 131
14
0
A Channel 4–
3.3V
GND
-
15
-
-
GND
-
16
-
-
F_LVDS_A5_P 121
17
1
A Channel 5+
3.3V
F_LVDS_A5_N 120
18
1
A Channel 5–
3.3V
GND
-
19
-
-
GND
-
20
-
-
Table 3-12 J4 FPGA Pinout
Signal Name
Pin No.
Socket Pin No.
BANK
Description
I/O
F_LVDS_B1_P 119
1
1
B Channel 1
3.3V
F_LVDS_B1_N 118
2
1
B Channel 1–
3.3V
GND
-
3
-
-
-
GND
-
4
-
-
-
F_LVDS_B2_P 117
5
1
B Channel 2+
3.3V
