2 Development Board Description
2.6 Development Board Specification
DBUG405-1.0E
7(25)
2.6
Development Board Specification
Table 2-1 Development Board Specification
No. Item
Functions
Technical Conditions
Note
1
FPGA
Core chip
–
–
2
Download
Support an USB
interface; Support
JTAG, MSPI, and
Multi BOOT
USB-JTAG module on
board
–
3
Power Supply
3.3 V, 1.8V and 1.0 V
output via LDO circuit
Input power: 5V
Provide power for FPGA,
download circuit and other
circuits via 5V–3.3 V circuit;
Provide power for FPGA
PSRAM via 5V–1.8V circuit;
Provide power for FPGA via
5 V–1.0 V circuit.
–
4
Slide Switches
Available for testing
2
–
5
Key Switches
Available for testing
2
–
6
Reset button
Reset for FPGA
1
–
7
LED
Test indicator, DONE
indicator, Power
indicator
Four Test indicators, green
One DONE indicator, green
One Power indicator, green
–
8
Crystal
Oscillator
Provide 50MHz clock
for FPGA
Package5032
–
9
Memory
Offers PSRAM
64Mbit built-in PSRAM
–
10
GPIO
I/O, convenient for
user extension and
test
50
–
11
LVDS
LVDS, used for
testing
5 pairs of input, 5 pairs of
output
–
12
Ethernet
For design use.
2 Ethernet interfaces
–
13
Protection
USB interface: ESD
protection;
Power interface:
Inverse current and
over current
protection
USB interface ESD
protection: ±15kV
non-contact discharge, ±
8kV contact discharge;
Schottky diode is connected
between positive and
negative anodes of power
–
