2 Development Board Description
2.5 Features
DBUG405-1.0E
6(25)
2.5
Features
The structure and features of the development board are as follows:
1.
FPGA
EQFP144 package
Up to 120 user I/O
Abundant LUT4 resources
Multiple modes and capacities of BSRAM
2.
FPGA Configuration Mode
JTAG
MSPI
Multi BOOT
3.
Clock resource
50MHz Clock Crystal Oscillator
4.
Key switch and slide switch
One reset button
Two key switches
Two slide switches
5.
LED
One power indicator (green)
One DONE indicator (green)
Four LEDs (green)
6.
Memory
64Mbit built-in PSRAM
7.
LVDS
5 pairs of LVDS differential input; 5 pairs of LVDS differential output
8.
GPIO
50 I/O extented resources
9.
Ethernet
2 Ethernet interfaces
10.
LDO Power
Supports 3.3 V, 1.8V, and1.0V.
