GOWIN DK_START_GW2AR-LV18EQ144PC8I7, User Manual

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3 Development Board Circuit 3.5 LED
DBUG405-1.0E 13(25)
3.4.2 Clock, Reset
Figure 3-3 Clock, Reset
6
135
KEY3
50MHz
ADM811
3.3V
FPGA_RST_N
FPGA_CLK
U9
U7
X4
GW2AR-
LV18EQ144PC8I7
3.4.3 Pinout
Table 3-3 FPGA Clock and Reset Pinout
Signal Name Pin No. BANK Description I/O
FPGA_CLK 6 7 50MHz crystal oscillator Input 3.3V
FPGA_RST_N 135 0 Reset signal, active low 1.8V
3.5 LED
3.5.1 Overview
Four green LEDs are incorporated into the development board and are
used to display the required status. In addition, two LEDs are reserved to
signify power supply and FPGA loading status.
Users can test the LEDs in the following ways:

If the output signal of related pins is logic low, LED is on.

If the logic is high, LED is off.
3.5.2 LED Circuit
Figure 3-4 LED Circuit
LED1
124
LED2
125
LED3 126
LED4 128
VCC3P3
F_LED1
F_LED2
F_LED3
F_LED4
U9
GW2AR-
LV18EQ144PC8I7