3 Development Board Circuit
3.9 LVDS
DBUG405-1.0E
19(25)
Signal Name Pin No.
Socket Pin No.
BANK
Description
I/O
H_B_IO8
122
5
0
General I/O
3.3V
-
-
6
-
-
-
H_B_IO10
90
7
3
General I/O
3.3V
H_B_IO9
123
8
0
General I/O
3.3V
H_B_IO12
87
9
3
General I/O
3.3V
H_B_IO11
92
10
3
General I/O
3.3V
H_B_IO14
85
11
3
General I/O
3.3V
H_B_IO13
88
12
3
General I/O
3.3V
H_B_IO16
83
13
3
General I/O
3.3V
H_B_IO15
86
14
3
General I/O
3.3V
H_B_IO18
80
15
3
General I/O
3.3V
H_B_IO17
84
16
3
General I/O
3.3V
H_B_IO20
78
17
3
General I/O
3.3V
H_B_IO19
82
18
3
General I/O
3.3V
H_B_IO22
76
19
3
General I/O
3.3V
H_B_IO21
79
20
3
General I/O
3.3V
3.9
LVDS
3.9.1
Overview
Two 2.0 mm DC3-20P sockets are reserved on the development board
for LVDS input/output testing and data communication.
3.9.2
LVDS Circuit
Figure 3-8 LVDS Circuit
1
3
5
7
9
2
4
6
8
10
11
13
15
17
19
12
14
16
18
20
F_LVDS_A1_P
F_LVDS_A2_P
F_LVDS_A3_P
F_LVDS_A4_P
F_LVDS_A5_P
F_LVDS_A1_N
F_LVDS_A2_N
F_LVDS_A3_N
F_LVDS_A4_N
F_LVDS_A5_N
J3
1
3
5
7
9
2
4
6
8
10
11
13
15
17
19
12
14
16
18
20
F_LVDS_B1_P
F_LVDS_B2_P
F_LVDS_B3_P
F_LVDS_B4_P
F_LVDS_B5_P
F_LVDS_B1_N
F_LVDS_B2_N
F_LVDS_B3_N
F_LVDS_B4_N
F_LVDS_B5_N
J4
