GOWIN DK_START_GW2A-LV18PG256C8I7_V2.0 User Manual Download Page 3 | Manualshive

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Revision History

Date

Version

Description

01/20/2021

1.0E

Initial version published.

09/10/2021

1.1E

The Quick Start in 2.2 A Development Board Suite removed.

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Summary of Contents for DK_START_GW2A-LV18PG256C8I7_V2.0

Page 1: ...DK_START_GW2A LV18PG256C8I7_V2 0 RISC V DEMO_B User Guide DBUG385 1 1E 09 10 2021 ...

Page 2: ... mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions ...

Page 3: ...Revision History Date Version Description 01 20 2021 1 0E Initial version published 09 10 2021 1 1E The Quick Start in 2 2 A Development Board Suite removed ...

Page 4: ...ack 2 2 Development Board Description 3 2 1 Overview 3 2 2 A Development Board Suite 4 2 3 PCB Components 5 2 4 System Architecture 5 2 5 Features 6 3 Development Board Circuit 8 3 1 FPGA Module 8 3 2 Download Module 8 3 2 1 Introduction 8 3 2 2 Pinsout 9 3 3 Power Supply 9 3 3 1 Introduction 9 3 3 2 Power System Distribution 10 3 4 Clock Reset 11 3 4 1 Introduction 11 3 4 2 Pinout 11 3 5 DDR3 11 ...

Page 5: ...S interfaces 15 3 7 1 Introduction 15 3 7 2 Pinout 16 3 8 SD Card 17 3 8 1 Introduction 17 3 8 2 Pinout 17 3 9 GPIO 18 3 9 1 Introduction 18 3 9 2 Pinout 19 3 10 LED 20 3 10 1 Introduction 20 3 10 2 Pinout 20 3 11 Key 21 3 11 1 Introduction 21 3 11 2 Pinout 21 3 12 Switch 21 3 12 1 Introduction 21 3 12 2 Pinout 22 4 Gowin Software 23 ...

Page 6: ...10 Figure 3 3 Connection Diagram of Clock and Reset 11 Figure 3 4 Connection Diagram of FPGA and DDR3 12 Figure 3 5 Connection Diagram of FPGA and Ethernet 14 Figure 3 6 LVDS TX Interface 15 Figure 3 7 LVDS RX Interface 16 Figure 3 8 Connection Diagram of SD Card 17 Figure 3 9 20 pin Interface 18 Figure 3 10 30 pin Interface 18 Figure 3 11 LED Connection 20 Figure 3 12 GPIO Circuit 21 Figure 3 13 ...

Page 7: ...out 9 Table 3 2 Clock and Reset Pinout 11 Table 3 3 DDR3 Pinout 12 Table 3 4 Ethernet Pinout 14 Table 3 5 LVDS TX Interface Pinout 16 Table 3 6 LVDS RX Interface Pinout 16 Table 3 7 20 pin Interface Pinout 19 Table 3 8 30 pin Interface Pinout 19 Table 3 9 LED Pinout 20 Table 3 10 Key Pinout 21 Table 3 11 Switch Pinout 22 ...

Page 8: ... functions circuits and pins distribution An introduction to the use of the Gowin Software 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS102 GW2A series of FPGA Products Data Sheet 2 UG110 GW2A 18 Pinout 3 UG111 GW2A series of FPGA Products Package and Pinout 4 SUG100 Gowin Software User Guide 1 3 Abb...

Page 9: ...mable I O LDO Low Dropout Regulator LUT4 4 input Look up Table LVDS Low Voltage Differential Signaling SSRAM Shadow Static Random Access Memory 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly using the information provided below Website www gowinsemi com E ...

Page 10: ...ication of hardware reliability software learning and debugging etc The development board uses the GW2A LV18PG256 FPGA device which is the first generation product of Gowin Arora family The GW2A series of FPGA products offer a range of comprehensive features and rich internal resources like high performance DSP resources a high speed LVDS interface and abundant BSRAM memory resources These embedde...

Page 11: ...nication It has abundant peripheral interfaces including LVDS interfaces a SD card slot and GPIO interfaces Besides that it also offers an external Flash slide switches key switches external clocks etc 2 2 A Development Board Suite A development board suite includes the following items 1 DK_START_GW2A LV18PG256C8I7_V2 0 development board 2 5V power adaptor Input 100 240V 50 60Hz 0 5A output DC 5V ...

Page 12: ...LASH SD Card Reset Key External Clock Key 4 LVDS TX FPGA LVDS RX USB to JTAG Chip Switch 4 Power Socket Power Switch 20PIN GPIO 30PIN GPIO MODE BANK7 Level Selection LED 4 USB MINI B 2 4 System Architecture Figure 2 2 System Architecture DDR3 2Gbit LED Switches Crystal Oscillator JTAG EthernetI nterface 1 EthernetI nterface 2 20PIN GPIO Header 30PIN GPIO Header Configure FLASH X16 X24 SD Card X31 ...

Page 13: ...opment board generates 3 3V 2 5V 1 5V 1 2V 1 0V and 0 75V required by DDR3 4 Clock system 50MHz crystal oscillator Input External signals input 5 Memory device 2Gbit DDR3 SDRAM 64Mbit FLASH 6 Ethernet interface Two Ethernet interfaces Supports 10M 100M 1000M RJ45 connector with built in transformer 7 LVDS interfaces One LVDS interface for receiving including five pairs of differential signals One ...

Page 14: ...k voltage can be adjusted as 3 3V 2 5V 1 2V one 3 3V voltage one 5V voltage and two ground pins 30PIN double row pins including 24 GPIO one 2 5V I O Bank voltage one 3 3V voltage one 5V voltage and three ground pins Note For the V2 0 development board the BANK0 voltage and BANK1 voltage can be set as 3 3V or 2 5V using J13 10 Debugging module Four keys Four switches Four blue LEDs ...

Page 15: ...ownload interface You can set the MODE value to download the programs to the on chip SRAM or external Flash When downloaded to SRAM the data stream file will be lost if the device is power down When downloaded to Flash the data stream file will not be lost The MODE value configuration 1 In any modes you can download the data stream file to the on chip SRAM and run it immediately 2 Set MODE as 011 ...

Page 16: ...TMS B8 2 3 3V JTAG Signal FLASH_SPI_MISO P10 3 3 3V FLASH signal configuration FLASH_SPI_MOSI R10 3 3 3V FLASH signal configuration FLASH_SPI_CS_N M9 3 3 3V FLASH signal configuration FLASH_SPI_CLK L10 3 3 3V FLASH signal configuration 3 3 Power Supply 3 3 1 Introduction 5V power Input 100 240V 50 60MHz 0 5A output DC 5V 2A The development board generates 3 3V 2 5V 1 5V 1 2V 1 0V and 0 75V require...

Page 17: ... 3V 1 5V 1 0V 2A TPS51200 DDR Terminal Regulator 0 75V VDDQ VDD DDR3 VREFDQ VREFCA DDR3 Pull up power of singal line DDR3 VCC VCCPLLL VCCPLLR FPGA VCCO0 VCCO1 VCCO7 FPGA VCCO2 VCCO3 VCCO7 VCCX FPGA VCCO4 VCCO5 VCCO6 FPGA VCCO7 FPGA 30PIN GPIO Pin 20PIN GPIO Pin Ethernet Interface Chip1 B50610KML Ethernet Interface Chip2 B50610KML USB to JTAG FT2232 Configure FLASH W25Q64 SD Card Keys Switches LED ...

Page 18: ... The 3 3V voltage is monitored in real time The reset signal will be generated once an exception occurs The reset signal can also be generated via the reset key Figure 3 3 Connection Diagram of Clock and Reset H11 T15 T10 KEY1 50MHz ADM811 EXT CLK 3 3V RST_N CLK_SMA CLK_G 3 4 2 Pinout Table 3 2 Clock and Reset Pinout Signal Name FPGA Pin No BANK I O Description CLK_G H11 0 2 5V 50MHz crystal oscil...

Page 19: ...ignal Name FPGA Pin No BANK I O Description DDR3_A0 F7 6 1 5V Address DDR3_A1 A4 5 1 5V Address DDR3_A2 D6 5 1 5V Address DDR3_A3 F8 6 1 5V Address DDR3_A4 C4 6 1 5V Address DDR3_A5 E6 6 1 5V Address DDR3_A6 B1 5 1 5V Address DDR3_A7 D8 6 1 5V Address DDR3_A8 A5 5 1 5V Address DDR3_A9 F9 6 1 5V Address DDR3_A10 K3 4 1 5V Address DDR3_A11 B7 6 1 5V Address DDR3_A12 A3 5 1 5V Address DDR3_A13 C8 6 1...

Page 20: ...ta DDR3_DQ6 E1 5 1 5V Data DDR3_DQ7 B3 5 1 5V Data DDR3_DQ8 M3 4 1 5V Data DDR3_DQ9 K4 4 1 5V Data DDR3_DQ10 N2 4 1 5V Data DDR3_DQ11 L1 4 1 5V Data DDR3_DQ12 P4 4 1 5V Data DDR3_DQ13 H3 4 1 5V Data DDR3_DQ14 R1 4 1 5V Data DDR3_DQ15 M2 4 1 5V Data DDR3_LDM G1 5 1 5V Data input mask DDR3_LDQSn G3 5 1 5V Data strobe DDR3_LDQSp G2 5 1 5V Data strobe DDR3_ODT R3 4 1 5V On Die Termination Enable DDR3_...

Page 21: ...3 0 CLK_PHY1 PHY2 RST_N PHY_MDC PHY_MDIO PHY2_GTXCLK PHY2_RXC PHY2_TX_EN PHY2_RX_DV PHY2_TXD 3 0 PHY2_RXD 3 0 CLK_PHY2 GbE 2 GbE 1 25MHz 25MHz 3 6 2 Pinout Table 3 4 Ethernet Pinout Signal Name FPGA Pin No BANK I O Description PHY_MDC M10 2 3 3V Management channel clock PHY_MDIO N11 2 3 3V Manage channel data PHY1_GTXCLK N10 2 3 3V PHY1 Transmitter Clock PHY1_TXD0 P11 2 3 3V PHY1 sending data chan...

Page 22: ... 3 3V PHY2 receive data channel 0 PHY2_RXD1 R7 3 3 3V PHY2 receive data channel 1 PHY2_RXD2 R8 3 3 3V PHY2 receive data channel 2 PHY2_RXD3 T8 3 3 3V PHY2 receive data channel 3 PHY2_RX_DV T9 3 3 3V PHY2 receive data enable 3 7 LVDS interfaces 3 7 1 Introduction The LVDS interfaces are the two 20 contact pins with the pitch of 2 00mm One defaults to the transmitting interface The other one default...

Page 23: ...L14 1 2 5V Differential Channel 2 9 LVDS_B3_P N16 1 2 5V Differential Channel 3 10 LVDS_B3_N N14 1 2 5V Differential Channel 3 13 LVDS_B4_P N15 1 2 5V Differential Channel 4 14 LVDS_B4_N P16 1 2 5V Differential Channel 4 17 LVDS_B5_P P15 1 2 5V Differential Channel 5 18 LVDS_B5_N R16 1 2 5V Differential Channel 5 For the V2 0 development board J13 needs to be set as 2 5V when LVDS is used Table 3 ...

Page 24: ...rd slot on the board is the push push type with eight contacts It offers the detection of the card insertion The connection diagram is shown as follows Figure 3 8 Connection Diagram of SD Card SD Card Socket SD_D0 SD_CD D3 SD_D1 SD_CMD SD_D2 SD_CLK SD_SWITCH 3 8 2 Pinout Table 4 3 SD Card Pinout Signal Name FPGA Pin No BANK I O Description SD_D0 M8 3 3 3V Data bits 0 SD_D1 N8 3 3 3V Data bits 1 SD...

Page 25: ...1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 H_A_IO1 H_A_IO3 H_A_IO5 H_A_IO7 H_A_IO9 H_A_IO11 H_A_IO13 H_A_IO15 H_A_IO2 H_A_IO4 H_A_IO6 H_A_IO8 H_A_IO10 H_A_IO12 H_A_IO14 H_A_IO16 3 3V 5 0V J3 Figure 3 10 30 pin Interface 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 21 23 25 27 29 22 24 26 28 30 H_GPIO_01 H_GPIO_03 H_GPIO_05 H_GPIO_07 H_GPIO_09 H_GPIO_11 H_GPIO_13 H_GPIO_15 H_GPIO_02 H...

Page 26: ... 2 5V 1 2V General I O 15 H_A_IO13 E10 7 3 3V 2 5V 1 2V General I O 16 H_A_IO14 C9 7 3 3V 2 5V 1 2V General I O 17 H_A_IO15 A9 7 3 3V 2 5V 1 2V General I O 18 H_A_IO16 F10 7 3 3V 2 5V 1 2V General I O Table 3 8 30 pin Interface Pinout Pin No Signal Name FPGA Pin No BANK I O Description 5 H_GPIO_01 M14 1 2 5V General I O 6 H_GPIO_02 K12 1 2 5V General I O 7 H_GPIO_03 J13 0 2 5V General I O 8 H_GPIO...

Page 27: ...r the V2 0 development board the BANK0 voltage and BANK1 voltage can be set as 3 3V or 2 5V using J13 3 10 LED 3 10 1 Introduction Four blue LEDs are incorporated into the development board and are used to display the required status If the output signal of the related pins is logic low LED is on If logic is high LED is off The connection diagram is shown in Figure 3 11 Figure 3 11 LED Connection ...

Page 28: ... control input during testing The connection diagram is shown in Figure 3 12 Figure 3 12 GPIO Circuit T2 T3 T4 T5 KEY1 KEY2 KEY3 KEY4 3 11 2 Pinout Table 3 10 Key Pinout Signal Name FPGA Pin No BANK I O Description KEY1 T2 4 1 5V KEY1 KEY2 T3 4 1 5V KEY2 KEY3 T4 4 1 5V KEY3 KEY4 T5 4 1 5V KEY4 3 12 Switch 3 12 1 Introduction Four slide switches are incorporated into the development board These are...

Page 29: ... 23 Figure 3 13 GPIO Circuit SW1 E9 SW2 E8 SW3 C7 SW4 D7 1 5V 3 12 2 Pinout Table 3 11 Switch Pinout Signal Name FPGA Pin No BANK I O Description SW1 E9 6 1 5V Slide Switch1 SW2 E8 6 1 5V Slide Switch2 SW3 C7 6 1 5V Slide Switch3 SW4 D7 6 1 5V Slide Switch4 ...

Page 30: ...4 Gowin Software DBUG385 1 1E 23 23 4 Gowin Software For the details you can see SUG100 Gowin Software User Guide ...

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