3 Development Board Circuit
3.1 FPGA Module
DBUG385-1.1E
8(23)
3
Development Board Circuit
3.1
FPGA Module
Overview
For the resources of GW2A series of FPGA Products, please refer to
GW2A series of FPGA Products Data Sheet
.
I/O BANK Introduction
For the I/O BANK, package and pinout information, please refer to
GW2A series of FPGA Products Package and Pinout
.
3.2
Download Module
3.2.1
Introduction
The development board offers a USB download interface. You can set
the MODE value to download the programs to the on-chip SRAM or
external Flash. When downloaded to SRAM, the data stream file will be lost
if the device is power down. When downloaded to Flash, the data stream
file will not be lost.
The MODE value configuration:
1.
In any modes, you can download the data stream file to the on-chip
SRAM and run it immediately.
2.
Set MODE as "011" to download the data stream file to the external
Flash. Set MODE as "000", and when power-on again, the device will
read the FPGA configuration data from the Flash automatically.
The connection diagram for downloading and configuration is as
follows.
