3 Development Board Circuit
3.7 LVDS interfaces
DBUG385-1.1E
15(23)
Signal Name
FPGA Pin No. BANK I/O
Description
PHY1_RXD2
R13
2
3.3V
PHY1 receive data channel 2
PHY1_RXD3
T14
2
3.3V
PHY1 receive data channel 3
PHY1_RX_DV
R14
2
3.3V
PHY1 receive data enable
PHY2_GTCLK
T7
3
3.3V
PHY2 Transmitter Clock
PHY2_TXD0
M6
3
3.3V
PHY2 sending data channel 0
PHY2_TXD1
N6
3
3.3V
PHY2 sending data channel 1
PHY2_TXD2
P6
3
3.3V
PHY2 sending data channel
2
PHY2_TXD3
M7
3
3.3V
PHY2 sending data channel 3
PHY2_TX_EN
P8
3
3.3V
PHY2 sending data enable
PHY2_RXC
N7
3
3.3V
PHY2 Clock receive
PHY2_RXD0
P7
3
3.3V
PHY2 receive data channel 0
PHY2_RXD1
R7
3
3.3V
PHY2 receive data channel 1
PHY2_RXD2
R8
3
3.3V
PHY2 receive data channel 2
PHY2_RXD3
T8
3
3.3V
PHY2 receive data channel 3
PHY2_RX_DV
T9
3
3.3V
PHY2 receive data enable
3.7
LVDS interfaces
3.7.1
Introduction
The LVDS interfaces are the two 20 contact pins with the pitch of
2.00mm. One defaults to the transmitting interface. The other one defaults
to the receiving interface. Each interface includes five pairs of differential
signals. The terminating resistor can be changed to modify the transmitting
and receiving attributes, as shown in the figure below.
Figure 3-6 LVDS TX Interface
1
3
5
7
9
2
4
6
8
10
11
13
15
17
19
12
14
16
18
20
LVDS_B1_P
LVDS_B2_P
LVDS_B3_P
LVDS_B4_P
LVDS_B5_P
LVDS_B1_N
LVDS_B2_N
LVDS_B3_N
LVDS_B4_N
LVDS_B5_N
J10
