GOWIN DK-START-GW2A55-PG484 V1.3 User Manual Download Page 15

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2 Introduction

2.5 Features

DBUG375-1.2E

6(34)

2.5

Features

The key features are as follows:

The FPGA device



Gowin GW2A-LV55PG484 FPGA



Max. user I/O 319

Download and Boot



Integrates the download module and can be downloaded with USB
Mini B cable



External Flash boot



The blue DONE light is on after loading.

Power



External DC 5V 2A



The blue POWER light is on after power on.



The development board generates 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, 1.0v,
0.75v and the power needed by LCD interface and MIPI interface.

Clock system
50MHz crystal oscillator input

Memory Device



2Gbit DDR3 SDRAM



64Mbit FLASH

Ethernet interface



Two Ethernet interfaces



Supports RGMII (10/100/1000) interface.



RJ45 connector integrating transformer

LVDS interfaces



Two LVDS interfaces for receiving, including ten pairs of differential
signals.



Two LVDS interface for sending, including ten pairs of differential
signals.



I/O voltage is adjustable when used as GPIO, supporting 3.3v, 2.5v
and 1.8v.

Note!

J13 needs to be set to 2.5V when LVDS is used.

MIPI DSI Interface



The interface includes 5 pairs of differential signals, among which
one for clock and four for data.



The stacked board connector with 30 contacts, 0.4mm pitch is
used.



Five lane DSI signals are simultaneously channeled to 20pin

Summary of Contents for DK-START-GW2A55-PG484 V1.3

Page 1: ...DK START GW2A55 PG484_V1 3 User Guide DBUG375 1 2E 09 01 2021 ...

Page 2: ... mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions ...

Page 3: ...sion Description 04 22 2020 1 0E Initial version published 01 06 2020 1 1E The name of the board updated The description of chapter 3 1 FPGA Module updated 09 01 2021 1 2E The quick start in 2 2 Development Board Suite removed ...

Page 4: ... 1 1 4 Support and Feedback 2 2 Introduction 3 2 1 Overview 3 2 2 Development Board Suite 4 2 3 PCB Components 5 2 4 System Block Diagram 5 2 5 Features 6 3 Development Board Circuit 8 3 1 FPGA Module 8 3 2 Download Module 8 3 2 1 Introduction 8 3 2 2 Pinout 9 3 3 Power Supply 10 3 3 1 Introduction 10 3 4 Clock and Reset 11 3 4 1 Introduction 11 3 4 2 Pinout 11 3 5 DDR3 12 ...

Page 5: ...troduction 17 3 8 2 Pinout 18 3 9 MIPI CSI 19 3 9 1 Introduction 19 3 9 2 Pinout 20 3 10 SD Card 20 3 10 1 Introduction 20 3 10 2 Pinout 21 3 11 RTC 21 3 11 1 Introduction 21 3 11 2 Pinout 21 3 12 AD DA 22 3 12 1 Introduction 22 3 12 2 Pinout 22 3 13 CAN 22 3 13 1 Introduction 22 3 13 2 Pinout 23 3 14 WIFI 23 3 14 1 Introduction 23 3 14 2 Pinout 23 3 15 GPIO 24 3 15 1 Introduction 24 3 15 2 Pinout...

Page 6: ...LED Module 29 3 17 1 Introduction 29 3 17 2 Pinout 29 3 18 Keys Module 29 3 18 1 Introduction 29 3 18 2 Pinout 30 3 19 Switches Module 30 3 19 1 Introduction 30 3 19 2 Pinout 31 4 Quick Start 32 4 1 Install Software 32 4 2 Development Board Power on Test 32 4 3 Build Demo Program 32 4 4 Download and Run 34 ...

Page 7: ...on Diagram of FPGA and Ethernet 14 Figure 3 6 LVDS TX Interface 15 Figure 3 7 LVDS RX Interface 16 Figure 3 8 Connection Diagram of MIPI DSI 18 Figure 3 9 Connection Diagram of MIPI CSI 19 Figure 3 10 Connection Diagram of SD Card 20 Figure 3 11 Connection Diagram of RTC 21 Figure 3 12 Connection Diagram of AD DA 22 Figure 3 13 Connection Diagram of CAN 23 Figure 3 14 Connection Diagram of WIFI 23...

Page 8: ...List of Figures DBUG375 1 2E v Figure 4 2 Process Window 33 Figure 4 3 Build Completed 33 Figure 4 4 Programmer Window 34 Figure 4 5 Device Configure Window 34 Figure 4 6 Click Program Configure 34 ...

Page 9: ... Table 3 8 LVDS TX2 Pinout 17 Table 3 9 LVDS TX2 Pinout 17 Table 3 10 MIPI DSI Pinout 18 Table 3 11 MIPI DSI Pinout 20 Table 3 12 SD Card Pinout 21 Table 3 13 RTC Pinout 21 Table 3 14 AD DA Pinout 22 Table 3 15 CAN Pinout 23 Table 3 16 WIFI Pinout 23 Table 3 17 40pin Interface Pinout 25 Table 3 18 20pin Interface Pinout 26 Table 3 19 50pin FPC Interface Pinout 28 Table 3 20 LCD Screen Brightness C...

Page 10: ...e resources An introduction to the hardware circuits functions and pinout 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com DS102 GW2A series FPGA Products Data Sheet UG113 GW2A 55 Pinout UG111 GW2A series of FPGA Products Package and Pinout User Guide UG290 Gowin FPGA Products Programming and Configuration G...

Page 11: ...ld Programmable Gate Array GPIO Gowin Programmable I O LDO Low Dropout Regulator LUT4 Four input Look up Table LVDS Low Voltage Differential Signaling SSRAM Shadow Static Random Access Memory 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ...

Page 12: ...on the verification of hardware reliability software learning and debugging etc The development board uses the GW2A LV55PG484 FPGA device which is the first generation product of Gowin Arora family The GW2A series of FPGA products offer a range of features and rich resources like high performance DSP high speed LVDS interface and BSRAM These embedded resources combine a streamlined FPGA architectu...

Page 13: ...AN bus interface MIPI CSI MIPI DSI AD DA interface and GPIO interfaces RTC module is designed to provide real time clock for MCU IP Besides that it also offers an external Flash switches keys LED etc 2 2 Development Board Suite The development board suite includes the following items 1 DK START GW2A55 PG484_V1 3 development board 2 5V power Input 100 240V 50 60Hz 0 5A output DC 5V 2A 3 USB Mini B ...

Page 14: ...r DDR3 1 5V Power 3 3V Power Power Socket Power Switch 40PIN GPIO LED 4 USB MINI B Switch 4 USB to JTAG Chip LVDS RX LVDS TX FPGA Key 4 Reset Configuration FLASH Bank4 Level Select SD 20PIN GPIO LCD Interface CAN Interface CSI DSI AD DA WIFI 1 2V Power 1 8V Power Dip Switch Ethernet 2 2 4 System Block Diagram Figure 2 4 System Block Diagram ...

Page 15: ...al oscillator input 5 Memory Device 2Gbit DDR3 SDRAM 64Mbit FLASH 6 Ethernet interface Two Ethernet interfaces Supports RGMII 10 100 1000 interface RJ45 connector integrating transformer 7 LVDS interfaces Two LVDS interfaces for receiving including ten pairs of differential signals Two LVDS interface for sending including ten pairs of differential signals I O voltage is adjustable when used as GPI...

Page 16: ... power supply or button cell The communication interface with FPGA is I2C 12 AD DA Supports 12 bit A D and D A converters and 8 channel interface can be configured to any combination of ADC DAC GPIO The input and output interface uses 8pin 13 CAN The communication with FPGA is via UART The maximum rate is 1Mbps 14 WIFI The communication with FPGA is via SPI SPI rate is 20Mbps 15 GPIO Interface The...

Page 17: ... of FT2232 USB conversion chip You can set the MODE value to download the programs to the on chip SRAM or external Flash When downloaded to SRAM the data stream file will be lost if the device is power down When downloaded to Flash the data stream file will not be lost if power down The MODE value configuration is as follows 1 In any modes you can download the data stream file to the on chip SRAM ...

Page 18: ...s an asynchronous FIFO interface The connection diagram is follows Figure 3 2 Asynchronous FIFO Connection Diagram EEDATA EECLK EECS FTDI_RD FTDI_TXE FTDI_RXF FIFO_D 7 0 USB to FIFO USB_D USB_D Configuration EEPROM FTDI_SIWU FTDI_WR 3 2 2 Pinout Table 3 1 FPGA Download and Pinout Name FPGA Pin No BANK I O Level Description JTAG_TCK N20 2 3 3V JTAG Signal JTAG_TDO M22 2 3 3V JTAG Signal JTAG_TDI M2...

Page 19: ...bit 2 FIFO_D3 F19 2 3 3V Data bit 3 FIFO_D4 G20 2 3 3V Data bit 4 FIFO_D5 G19 2 3 3V Data bit 5 FIFO_D6 H20 2 3 3V Data bit 6 FIFO_D7 H18 2 3 3V Data bit 7 3 3 Power Supply 3 3 1 Introduction The development board is powered through a power adapter The input parameter is 100 240V 50 60MHz 0 5A and the output is DC 5V 2A The input 5V power can generate 3 3v 2 5v 1 8v 1 5v 1 2v 1 0v and 0 75v power ...

Page 20: ...ing 3 4 Clock and Reset 3 4 1 Introduction The development board offers a 50MHz oscillator connecting to the global clock pins The reset circuit uses keys and dedicated reset chips After power on the reset chip automatically generates a reset signal to reset the FPGA and Ethernet PHY chip 3 3V voltage is monitored in real time and the reset signal is generated immediately when the exception occurs...

Page 21: ...Pinout Table 3 4 DDR3 Pinout Name FPGA Pin No BANK I O Level Description DDR3_A0 G1 7 1 5V Address DDR3_A1 U5 6 1 5V Address DDR3_A2 G5 7 1 5V Address DDR3_A3 F5 7 1 5V Address DDR3_A4 V3 6 1 5V Address DDR3_A5 G2 7 1 5V Address DDR3_A6 AA22 3 1 5V Address DDR3_A7 H5 7 1 5V Address DDR3_A8 AB22 3 1 5V Address DDR3_A9 J4 7 1 5V Address DDR3_A10 R5 6 1 5V Address DDR3_A11 AA21 3 1 5V Address DDR3_A1...

Page 22: ...Data DDR3_DQ4 Y1 6 1 5V Data DDR3_DQ5 U1 6 1 5V Data DDR3_DQ6 N3 6 1 5V Data DDR3_DQ7 V1 6 1 5V Data DDR3_DQ8 T1 7 1 5V Data DDR3_DQ9 K3 7 1 5V Data DDR3_DQ10 P1 7 1 5V Data DDR3_DQ11 J1 7 1 5V Data DDR3_DQ12 L5 7 1 5V Data DDR3_DQ13 H3 7 1 5V Data DDR3_DQ14 M1 7 1 5V Data DDR3_DQ15 H1 7 1 5V Data DDR3_LDM R3 6 1 5V Data input mask DDR3_LDQSn R4 6 1 5V Data strobe DDR3_LDQSp P4 6 1 5V Data strobe ...

Page 23: ..._MDIO PHY2_GTXCLK PHY2_RXC PHY2_TX_EN PHY2_RX_DV PHY2_TXD 3 0 PHY2_RXD 3 0 CLK_PHY2 GbE 2 GbE 1 25MHz 25MHz 3 6 2 Pinout Table 3 5 Ethernet Pinout Name FPGA Pin No BANK I O Level Description PHY_MDC H19 2 3 3V Manage channel clock PHY_MDIO J18 2 3 3V Manage channel data PHY1_GTCLK H21 2 3 3V PHY1 Transmit Clock PHY1_TXD0 H22 2 3 3V PHY1 transmitting data channel 0 PHY1_TXD1 G21 2 3 3V PHY1 transmi...

Page 24: ...ing data channel 0 PHY2_RXD1 L19 2 3 3V PHY2 receiving data channel 1 PHY2_RXD2 J20 2 3 3V PHY2 receiving data channel 2 PHY2_RXD3 K19 2 3 3V PHY2 receiving data channel 3 PHY2_RX_DV K18 2 3 3V PHY2 receiving data enable 3 7 LVDS Interfaces 3 7 1 Introduction The LVDS interfaces are the four 20 pins with the pitch of 2 00mm two of which are transmitting interfaces and the other are receiving inter...

Page 25: ...V Differential Channel 2 9 LVDS_B3_P Y19 4 2 5V Differential Channel 3 10 LVDS_B3_N Y18 4 2 5V Differential Channel 3 13 LVDS_B4_P AA17 4 2 5V Differential Channel 4 14 LVDS_B4_N Y17 4 2 5V Differential Channel 4 17 LVDS_B5_P AB16 4 2 5V Differential Channel 5 18 LVDS_B5_N AA16 4 2 5V Differential Channel 5 Table 3 7 LVDS TX2 Pinout Pin No Name FPGA Pin No BANK I O Level Description 1 LVDS_B6_P AB...

Page 26: ... No BANK I O Level Description 1 LVDS_A6_P Y14 4 2 5V Differential Channel 6 2 LVDS_A6_N Y15 4 2 5V Differential Channel 6 5 LVDS_A7_P W14 4 2 5V Differential Channel 7 6 LVDS_A7_N W15 4 2 5V Differential Channel 7 9 LVDS_A8_P AB13 4 2 5V Differential Channel 8 10 LVDS_A8_N AB14 4 2 5V Differential Channel 8 13 LVDS_A9_P Y12 4 2 5V Differential Channel 9 14 LVDS_A9_N Y13 4 2 5V Differential Channe...

Page 27: ... 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 DSI_D0p DSI_D1p DSI_CLKp DSI_D2p DSI_D3p DSI_D0n DSI_D1n DSI_CLKn DSI_D2n DSI_D3n J7 3 8 2 Pinout Table 3 10 MIPI DSI Pinout Name FPGA Pin No BANK I O Level Description DSI_D0n B22 1 2 5V HS differential data 0 DSI_D0p A22 1 2 5V HS differential data 0 DSI_D1n C19 1 2 5V HS differential data 1 DSI_D1p C18 1 2 5V HS differential data 1 DSI_CLKn A19 ...

Page 28: ...nal DSI_TE D16 1 2 5V Tearing effect output signal 3 9 MIPI CSI 3 9 1 Introduction MIPI CSI uses 15pin connector with 1mm pitch The interface includes 3 pairs of differential signals among which one for clock and two for data Differential signals of three lanes are simultaneously channeled to the double rows pin of 20pin with 2 00mm pitch Figure 3 9 Connection Diagram of MIPI CSI 1 J25 10 2 3 4 5 ...

Page 29: ... 0 CSI_LP_D0p A3 0 1 2V LP single ended data 0 CSI_LP_D1n A1 0 1 2V LP single ended data 1 CSI_LP_D1p B1 0 1 2V LP single ended data 1 CSI_LP_CLKn C4 0 1 2V LP single ended clock CSI_LP_CLKp C5 0 1 2V LP single ended clock CSI_RESET C21 2 3 3V Reset signal CSI_CLK C20 2 3 3V Clock CSI_SCL D19 2 3 3V I2C signal CSI_SDA G17 2 3 3V I2C signal 3 10 SD Card 3 10 1 Introduction The SD card slot on the b...

Page 30: ... 3 11 RTC 3 11 1 Introduction The real time clock module uses a chip that is externally connected with 32 768kHz quartz crystal It can be powered by the board power supply and the button battery The communication interface with the FPGA is I2C The connection diagram is follows Figure 3 11 Connection Diagram of RTC RTC Module RTC_INT IIC_SDA RTC_CLK IIC_SCL 3 11 2 Pinout Table 3 13 RTC Pinout Name ...

Page 31: ...e 3 12 Connection Diagram of AD DA IIC_SDA RTC_CLK AD DA_A0 AD DA_D0 AD DA_D1 AD DA_D2 AD DA_D3 AD DA_D4 AD DA_D5 AD DA_D6 AD DA_D7 AD DA Module 1 3 5 7 2 4 6 8 AD DA_D0 AD DA_D1 AD DA_D2 AD DA_D3 AD DA_D4 AD DA_D5 AD DA_D6 AD DA_D7 3 12 2 Pinout Table 3 14 AD DA Pinout Name FPGA Pin No BANK I O Level Description AD DA_A0 E14 1 2 5V Address input IIC_SCL A13 1 2 5V I2C signal IIC_SDA C13 1 2 5V I2...

Page 32: ...ta 3 14 WIFI 3 14 1 Introduction The WIFI module supports SPI and UART SPI transmission rate is 20Mbps The connection diagram is as follows Figure 3 14 Connection Diagram of WIFI WIFI Module WIFI_SPI_CLK WIFI_SPI_CS WIFI_SPI_MISO WIFI_TX WIFI_SPI_MOSI WIFI_RX 3 14 2 Pinout Table 3 16 WIFI Pinout Name FPGA Pin No BANK I O Level Description WIFI_SPI_CLK D9 0 1 2V SPI clock WIFI_SPI_MISO A10 0 1 2V S...

Page 33: ...k5 The I O level is 3 3v 20pin interface and 40pin multiplex GPIO Figure 3 15 40pin Diagram 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 21 23 25 27 29 22 24 26 28 30 31 33 35 37 39 32 34 36 38 40 3 3V H_GPIO_03 H_GPIO_05 H_GPIO_07 H_GPIO_09 H_GPIO_11 H_GPIO_13 H_GPIO_15 H_GPIO_17 H_GPIO_19 H_GPIO_21 H_GPIO_23 H_GPIO_01 H_GPIO_25 H_GPIO_27 H_GPIO_29 H_GPIO_31 H_GPIO_33 H_GPIO_04 H_GPIO_06 H_...

Page 34: ...I O 5 H_GPIO_03 AB11 5 3 3V General I O 6 H_GPIO_04 V9 5 3 3V General I O 7 H_GPIO_05 Y11 5 3 3V General I O 8 H_GPIO_06 Y3 5 3 3V General I O 9 H_GPIO_07 V10 5 3 3V General I O 10 H_GPIO_08 W11 5 3 3V General I O 11 H_GPIO_09 W10 5 3 3V General I O 12 H_GPIO_10 Y10 5 3 3V General I O 13 H_GPIO_11 W9 5 3 3V General I O 14 H_GPIO_12 Y8 5 3 3V General I O 15 H_GPIO_13 Y9 5 3 3V General I O 16 H_GPIO...

Page 35: ...33 AB2 5 3 3V General I O 36 H_GPIO_34 AB1 5 3 3V General I O Table 3 18 20pin Interface Pinout Pin No Name FPGA Pin No BANK I O Level Description 3 H_GPIO_01 AA11 5 3 3V General I O 4 H_GPIO_11 W9 5 3 3V General I O 5 H_GPIO_02 V11 5 3 3V General I O 6 H_GPIO_03 AB11 5 3 3V General I O 7 H_GPIO_04 V9 5 3 3V General I O 8 H_GPIO_12 Y8 5 3 3V General I O 9 H_GPIO_05 Y11 5 3 3V General I O 10 H_GPIO...

Page 36: ... multiplex GPIO of FPGA Figure 3 17 50pin FPC Interface Diagram 1 J23 10 2 3 4 5 6 7 8 9 11 20 12 13 14 15 16 17 18 19 21 30 22 23 24 25 26 27 28 29 31 40 32 33 34 35 36 37 38 39 41 50 42 43 44 45 46 47 48 49 LCD_MODE LCD_VS LCD_DE LCD_B7 LCD_HS LCD_B5 LCD_B6 LCD_B3 LCD_B4 LCD_B2 LCD_G7 LCD_G5 LCD_G6 LCD_G3 LCD_G4 LCD_G2 LCD_R7 LCD_R5 LCD_R6 LCD_R3 LCD_R4 LCD_DCLK LCD_U D LCD_R L LCD_RST LCD_VCOM ...

Page 37: ...17 LCD_B2 W8 5 3 3V Blue data bit7 20 LCD_G7 V8 5 3 3V Green data bit7 21 LCD_G6 AB8 5 3 3V Green data bit7 22 LCD_G5 W7 5 3 3V Green data bit7 23 LCD_G4 AA7 5 3 3V Green data bit7 24 LCD_G3 AB7 5 3 3V Green data bit7 25 LCD_G2 AA6 5 3 3V Green data bit7 28 LCD_R7 AB6 5 3 3V Red data bit7 29 LCD_R6 AB5 5 3 3V Red data bit7 30 LCD_R5 Y5 5 3 3V Red data bit7 31 LCD_R4 Y4 5 3 3V Red data bit7 32 LCD_...

Page 38: ...n diagram is shown in Figure 3 18 Figure 3 18 LED Connection Diagram LED1 W20 LED2 W22 LED3 V22 LED4 U20 3 3V 3 17 2 Pinout Table 3 21 LED Pinout Name FPGA Pin No BANK I O Level Description LED1 W20 3 1 5V LED 1 LED2 W22 3 1 5V LED 2 LED3 V22 3 1 5V LED 3 LED 4 U20 3 1 5V LED 4 Note SSPI needs to be reused as GPIO 3 18 Keys Module 3 18 1 Introduction The development board has four keys that can be...

Page 39: ...Table 3 22 Keys Module Pinout Name FPGA Pin No BANK I O Level Description KEY1 V20 3 1 5V KEY1 KEY2 T18 3 1 5V KEY2 KEY3 U18 3 1 5V KEY3 KEY4 T17 3 1 5V KEY4 3 19 Switches Module 3 19 1 Introduction There are four switches on the development board to control input during testing Figure 3 20 Switch Circuit Diagram SW1 R18 SW2 AB21 SW3 R19 SW4 Y21 1 5V ...

Page 40: ...it 3 19 Switches Module DBUG375 1 2E 31 34 3 19 2 Pinout Table 3 23 Switches Module Pinout Name FPGA Pin No BANK I O Level Description SW1 R18 3 1 5V Switch1 SW2 AB21 3 1 5V Switch2 SW3 R19 3 1 5V Switch3 SW4 Y21 3 1 5V Switch4 ...

Page 41: ... it is powered on Plug the 5V power supply into the power socket of the development board and and switch to ON and MODE is set to 000 The four blue LED lights are flashing indicating that the development board can operate 4 3 Build Demo Program The LED test program is to demonstrate four LEDs streaming flashing Users can download this demo at Gowinsemi website Support Starter Kits and Development ...

Page 42: ... Design Window 2 Right click Place Route in the Process window and select Rerun All Figure 4 2 Process Window 3 After building the following information will be displayed The generated bitstream file is saved in LED_test impl pnr LED_test fs Figure 4 3 Build Completed ...

Page 43: ... will pop up Right click the device list and select Configure Device The Device configuration dialog box will pop up Figure 4 4 Programmer Window 2 Set the download mode as shown below and specify the bitstream file path Figure 4 5 Device Configure Window 3 After configuration click the Program Configure to download the program After finishing the four LEDs of the development board will streaming ...

Page 44: ......

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