3Development Board Circuit
3.5DDR3
DBUG354-1.0E
17
(
30
)
3.5.1
Introduction
The development board includes a DDR3 chip with 2Gbit storage
space,16 bits data bus width, and the highest data speed of 1600MT/s.
Figure 3-6 Connection Diagram of FPGA and DDR3
DDR3_BA[2..0]
DDR3_A[13..0]
DDR3 SDRAM
2Gbit
DDR3_DQ[15..0]
DDR3_UDQSn
DDR3_LDQSn
DDR3_UDQSp
DDR3_LDQSp
DDR3_UDM
DDR3_LDM
DDR3_CASn
DDR3_RASn
DDR3_WEn
DDR3_ODT
DDR3_CK_EN
DDR3_CSn
DDR3_RSTn
DDR3_CKn
DDR3_CKp
3.5.2
Pins Distribution
Table 3-5 DDR3 Pins Distribution
Signal Name
FPGA Pin No.
BANK
I/O
Description
DDR3_A0
F7
6
1.5V
Address
DDR3_A1
A4
5
1.5V
Address
DDR3_A2
D6
5
1.5V
Address
DDR3_A3
F8
6
1.5V
Address
DDR3_A4
C4
6
1.5V
Address
DDR3_A5
E6
6
1.5V
Address
DDR3_A6
B1
5
1.5V
Address
DDR3_A7
D8
6
1.5V
Address
DDR3_A8
A5
5
1.5V
Address
DDR3_A9
F9
6
1.5V
Address
DDR3_A10
K3
4
1.5V
Address
DDR3_A11
B7
6
1.5V
Address
DDR3_A12
A3
5
1.5V
Address
