3Development Board Circuit
3.2Download Module
DBUG354-1.0E
12
(
30
)
I/O BANK No.
Supply voltage
Functions
DONE
RECONFIG_N
READY
FASTRD_N
BANK4
1.5V
DDR3
Key
BANK5
1.5V
DDR3
BANK6
1.5V
DDR3
Switches
BANK7
3.3V, 2.5V, 1.2V
(Adjustable)
20PIN GPIO Interface
Note
!
For the V2.0 development board, the BANK0 voltage and BANK1 voltage can be set as
3.3V or 2.5V using J13.
3.2
Download Module
3.2.1
Introduction
The development board offers a USB download interface. You can set
the MODE value to download the programs to the on-chip SRAM or
external Flash. When downloaded to SRAM, the data stream file will be lost
if the device is power down. When downloaded to Flash, the data stream
file will not be lost.
The MODE value configuration:
1.
In any modes, you can download the data stream file to the on-chip
SRAM and run it immediately.
2.
Set MODE as "000" to download the data stream file to the external
Flash. When power-on again, the device will read the FPGA
configuration data from the Flash automatically.
The connection diagram for downloading and configuration is as
follows: