3Development Board Circuit
3.4Clock, Reset
DBUG354-1.0E
16
(
30
)
Note
！
For the V2.0 development board, the BANK0 voltage and BANK1
voltage can be set as 3.3V or 2.5V using J13.
3.4
Clock, Reset
3.4.1
Introduction
The development board offers a 50MHz oscillator, connecting to the
global clock pins. It also offers a female SMA seat for users to input the
external clock for multiple tests.
The reset circuit adopts keys and dedicated reset chips. After powered
on the device, the reset chip automatically generates a reset signal to reset
the FPGA and Ethernet PHY chip. The 3.3V voltage is monitored in real
time. The reset signal will be generated once an exception occurs. The
reset signal can also be generated via the reset key.
Figure 3-5 Connection Diagram for Clock and Reset
H11
T15
T10
KEY1
50MHz
ADM811
EXT CLK
3.3V
RST_N
CLK_SMA
CLK_G
3.4.2
Pins Distribution
Table 3-4 Clock and Reset Pins Distribution
Signal Name
FPGA Pin No.
BANK I/O
Description
CLK_G
H11
0
2.5V
50MHz crystal oscillator Input
CLK_SMA
T15
2
3.3V
External clock input
RST_N
T10
3
3.3V
Reset signal, active low
3.5
DDR3
