Giga-tronics 58542, Operation & Maintenance Manual

Page: 69 / 252

Operation
Publication 21555, Rev. E, September 2002 2-39
2.5.23 SRQ & Status Monitoring
■
*CLS
■
*ESE
■
*ESR?
■
*OPC
■
*OPC?
■
*SRE
■
STATus:OPERation
■
STATus:PREset
■
*STB?
*CLS
Example: OUTPUT @PWR_MTR;*CLS ! CLEARS SRQ AND STATUS BYTE REGISTERS
Description:
*CLS is the clear status command defined by IEEE 488.2. This command clears all of the
status bytes to the value 0. After a service request interrupt is transmitted from the 58542 to
the controller, use the *STB command to read the status byte from the 58542. Then reset the
SRQ and use *CLS clear status command to reset the numeric status indication of the status
byte/registers to 0 (all bits will be 0).
*CLS does not affect the enabled or disabled status of the status byte/register masks. For
example, having bit 8 of the operation register enabled before sending *CLS, it will remain
enabled afterward. *CLS also clears the output queue (takes 0.3 sec to complete this
function).
*ESE
Syntax: ESE space <event status register value, 0 to 255>
Example: OUTPUT @PWR_MTR;*ESE 16 ! ENABLES BIT 4 OF EVENT STATUS REGISTER MASK
Description:
This command sets/clears the event status register enable mask.
*ESR?
Example: OUTPUT @PWR_MTR;*ESR? ! RETURNS EVENT STATUS REGISTER VALUE
Description:
This query returns the current status register value.
*OPC
Example: OUTPUT @PWR_MTR;*OPC ! *OPC ALLOWS ONE TIME SRQ ENABLE
Description:
*OPC determines when an operation is completed. This command is generally used to
monitor the completion of long measurement sequences. It sets the operation complete bit in
the event status register upon completion of operation.
*OPC?
Example: OUTPUT @PWR_MTR;*OPC? ! RETURNS A VALUE OF 1 AFTER AN OPERATION IS
COMPLETED
Description:
The *OPC? operation complete query allows synchronization between the controller and the
test set using either the message available (MAV) bit in the status byte, or a read of the output
OPC?.