DIO24, User Manual
5. PLX PCI9080 Registers.......................................................................................................... 20
5.1. PCI Configuration Registers .............................................................................................................................20
5.1.1. PCI Configuration ID Register ...................................................................................................................20
5.1.2. PCI Command Register ..............................................................................................................................20
5.1.3. PCI Status Register.....................................................................................................................................21
5.1.4. PCI Revision ID Register ...........................................................................................................................22
5.1.5. PCI Class Code Register.............................................................................................................................22
5.1.6. PCI Cache Line Size Register ....................................................................................................................22
5.1.7. PCI Latency Timer Register .......................................................................................................................22
5.1.8. PCI Header Type Register..........................................................................................................................22
5.1.9. PCI Base Address Register for Memory Access to Local/Runtime/DMA Registers .................................22
5.1.10. PCI Base Address Register for I/O Access to Local/Runtime/DMA Registers........................................23
5.1.11. PCI Base Address Register for Memory Access to Local Address Space 0.............................................23
5.1.12. PCI Subsystem Device/Vendor ID Register.............................................................................................23
5.1.13. PCI Interrupt Line Register ......................................................................................................................23
5.1.14. PCI Interrupt Pin Register ........................................................................................................................23
5.1.15. PCI Min_Gnt Register..............................................................................................................................24
5.1.16. PCI Max_Lat Register..............................................................................................................................24
5.2. Local Configuration Registers ..........................................................................................................................24
5.2.1. Local Address Space 0 Range Register for PCI to Local Bus ....................................................................24
5.2.2. Mode/Arbitration Register..........................................................................................................................25
5.2.3. Big/Little Endian Descriptor Register ........................................................................................................25
5.2.4. Local Address Space 0/Expansion ROM Bus Region Descriptor Register................................................25
5.3. Runtime Registers.............................................................................................................................................26
5.3.1. Interrupt Control /Status .............................................................................................................................26
5.3.2. Serial EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register ........................27
5.3.3. PCI Permanent Configuration ID Register .................................................................................................27
5.3.4. PCI Permanent Revision ID Register .........................................................................................................27
5.4. DMA Registers .................................................................................................................................................28
5.5. Messaging Queue Registers ..............................................................................................................................28
Document History ....................................................................................................................... 29
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