DIO24, User Manual
2.3.1.1. PLX Default Configuration: J2:1-2
This jumper connects the PCI interface chip (the PLX PCI9080) to the On-board Configuration EEPROM (Serial
EEPROM U42). When the jumper is installed, the PCI interface chip will initialize some of its registers from the
content of the EEPROM. This initialization is necessary for correct PCI configuration. If the EEPROM becomes
corrupted, the invalid parameters can prevent proper host and DIO24 operation. Removing this jumper will force the
PCI interface chip into a default configuration that should allow PCI configuration to proceed. This will permit
proper host booting and allow for reprogramming of the EEPROM. In the default factory configuration this jumper
is installed.
WARNING:
This jumper should only be removed following factory consultation. The board will
not function correctly if this jumper is removed.
2.3.1.2. FPGA Reload: J2:3-4
This jumper connects the PCI reset signal to the FPGA chip. When the jumper is installed an FPGA reload occurs
(from EPROM U42) with each PCI reset (in compliance with the PCI spec). In the default factory configuration this
jumper is installed.
WARNING:
This jumper should only be removed following factory consultation.
2.3.1.3. User Jumper 0: J2:5-6
This jumper is provided for end user use. The jumper may be installed or removed at the user’s discretion and may
be read by examining bit 16 of the Board Status Register (described later). If the jumper is installed the bit returns a
one (1). If the jumper is removed the bit returns a zero (0). In the default factory configuration this jumper is
installed. One potential use of the jumper is to aid in distinguishing individual boards when multiple DIO24 boards
are installed.
2.3.1.4. User Jumper 1: J2:7-8
This jumper is provided for end user use. The jumper may be installed or removed at the user’s discretion and may
be read by examining bit 17 of the Board Status Register (described later). If the jumper is installed the bit returns a
one (1). If the jumper is removed the bit returns a zero (0). In the default factory configuration this jumper is
installed. One potential use of the jumper is to aid in distinguishing individual boards when multiple DIO24 boards
are installed.
2.4. Components
2.4.1. FPGA EPROM: U42
This EPROM contains the firmware for the DIO24 FPGA. The EPROM is located towards the center of the board’s
right edge. Pin one is at the upper left. The EPROM may be replaced with factory provided updates as needed.
NOTE:
The DIO24 can be outfitted with custom firmware on an as needed basis. Consult the
factory for additional information.
2.4.2. Termination Resistors: RP1 – RP7
Resister packs RP1 to RP7 are the termination resistors required for RS485 operation. They are located towards the
center of the board. Pin one is either at the top or the left of the socket, according to the socket’s orientation. For a
multi-drop environment the termination resistors are removed from all but the two end nodes. As necessary the
resistors may be also be replaced with alternate values. In the factory default configuration all seven resistor packs
are installed and all are 150
Ω
.
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