DIO24, User Manual
3. Operation
This section gives a brief description of the operation of the DIO24.
3.1. Identification
The DIO24 can be uniquely identified by examining the following list of registers. Full register descriptions are
given later in this document.
Table 4
Register level identification of the DIO24.
Register Value
Description
PCIIDR
0x908010B5
The lower 16-bits is the Vendor ID and identifies PLX Technology. The upper 16-
bits is the Device ID and identifies the chip is a PCI9080.
PCISVID
0x10B5
This identifies the board as a product of General Standards Corporation.
PCISID
0x2606
This identifies the board as a member of the DIO24 product series.
FRR
0xXX0BXXXX
The value in the third byte identifies this as a DIO24.
NOTE
: The PCI-DIO24-GD1 variation of the DIO24 has different identification register values,
as described in Table 2.
3.2. Reset
The board is reset by writing a one to the Reset bit of the GSC Board Control Register. The operation completes
within the given register write cycle. A reset programs all I/O pins as inputs and programs the data output latches to
zero.
3.3. I/O Programming
The I/O pins are programmed via the I/O Control Register. One bit controls Port A, another bit controls Port B and
eight additional bits individually control the eight Port C pins. Setting a bit to one programs the port/pin as an
output. Setting a bit to zero programs the port/pin as an input. Bits can be reprogrammed arbitrarily. The Dedicated
Input pin can be used as a single input or a clock output. Speed of the clock depends on the ordering option (clock
speed is specified in the part number).
3.4. I/O Reads and Writes
Reading from the Discrete Data Input Register (DDIR) will obtain the data level on all 25 pins, both input and
output. The data level on the output pins is control by the value written to the Discrete Data Output Register
(DDOR). Writes to the DDOR are latched. Reads from the DDOR return the current latched value. Propagation
delays from the external I/O connector to the DDIR, and from the DDOR to the external I/O connector are both less
than a single PCI bus access cycle.
15
General Standards Corporation, Phone: (256) 880-8787
