Gemalto Cinterion ELS31T-J, Hardware Interface Description, Page: 7 / 102

Cinterion
®
LTE Terminals Hardware Interface Description
Figures
7

ELSxT_HID_v04 2018-09-04
Confidential / Preliminary
Page 7 of 102
Figures
Figure 1: Product label of ELS61T-E.............................................................................. 18
Figure 2: Product Label of ELS61T-AUS ....................................................................... 18
Figure 3: Product label of ELS61T-US ........................................................................... 19
Figure 4: LTE Terminals 3D view ................................................................................... 24
Figure 5: Block diagram ................................................................................................. 25
Figure 6: LTE Terminals circuit block diagram ............................................................... 26
Figure 7: Pin assignment RS-232 (D-sub 9-pole female)............................................... 28
Figure 8: ELS61T-US/AUS: GPIO connectors (8-pin and 12-pin).................................. 29
Figure 9: ELS61T-E: GPIO connectors (8-pin and 12-pin)............................................. 30
Figure 10: ELS61T-E2: GPIO connectors (8-pin and 12-pin)........................................... 30
Figure 11: ELS31T-V/J: GPIO connectors (8-pin and 12-pin).......................................... 31
Figure 12: Long frame PCM timing, 256kHz .................................................................... 33
Figure 13: Block circuit for DAI/PCM to analog converter ................................................ 34
Figure 14: Sample circuit for analog to DAI/PCM circuit .................................................. 34
Figure 15: Audio Codec Board ......................................................................................... 35
Figure 16: Characteristics of SPI modes.......................................................................... 38
Figure 17: 8-pole RJ-45 Ethernet connector (female) ...................................................... 40
Figure 18: 6-pole Western jack for power supply, ignition, reset, typical connection ....... 41
Figure 19: SIM interface ................................................................................................... 45
Figure 20: Status LED ...................................................................................................... 46
Figure 21: Antenna connectors ........................................................................................ 47
Figure 22: LTE Terminals 3D overview ............................................................................ 61
Figure 23: LTE Terminals mechanical dimensions .......................................................... 62
Figure 24: LTE Terminals exploded view ......................................................................... 63
Figure 25: Mounting the LTE Terminals ........................................................................... 64
Figure 26: Reference equipment for approval.................................................................. 66
Figure 27: Hardware watchdog configuration................................................................... 73
Figure 28: Write data to address register ......................................................................... 90
Figure 29: Read data from address register..................................................................... 91
Figure 30: Setting GPIO direction to OUTPUT via I
2
C interface ...................................... 93
Figure 31: Setting GPIO direction to INPUT via I
2
C interface .......................................... 93
Figure 32: Setting GPIO direction to OUTPUT via TXD0 line (at 1200bps) ..................... 94
Figure 33: Setting GPIO direction to INPUT via TXD0 line (at 1200bps) ......................... 94