GE MAC 5000, Field Service Manual

Page: 75 / 160

Revision B 5-9
CPU Theory of Operation: Theory of Operation
MAC 5000 resting ECG analysis system
2000657-002
Interrupt Controller The StrongARM supports two external interrupts, FIQ (Fast Interrupt
Request) and IRQ (Interrupt ReQuest). The FPGA expands these inputs
to service numerous sources of interrupts in the FPGA internal logic and
SuperIO. Each interrupt source is routed to either the FIQ or IRQ pin
and is provided with a writeable enable bit and a readable status bit.
Note in particular that the FIQ status bits are masked by FIQ mask bits
whereas IRQ status bits are not. This reflects the different needs of the
FIQ and IRQ interrupt handlers.
System Interrupt Generator A 1KHz timer generates system interrupts (which may be routed to FIQ
or IRQ) once every millisecond. This interrupt provides the foundation
for all operating system timers.
Acquisition Module Interface Acquisition module timing is synchronized to the system clock. Data is
framed and checksummed. Commands may be sent without
interrupting the data stream. The acquisition module supports three
buttons whose state is communicated to the system in each ECG data
packet.
A constant reference clock frequency of 1MHz must be provided to the
acquisition module for generation of it’s internal sampling clocks. To
eliminate the need for extra wires, command information is encoded on
this reference clock by altering its duty cycle. The FPGA provides a
serializer for the command bytes and clock generator/modulator to
transmit both the clock and command bits from the serializer. The
reference clock duty cycle is nominally 50%. By altering the duty cycle,
the DC content of the clock may be changed. This change in DC level is
detected by the acquisition module. The timing of these shifts in DC
offset encode command data bits. A zero is encoded as a single shift in
duty cycle from 50% to 25% lasting 30µs, followed by a refractory period
of 220µs. A one is encoded as a pair of 30µs periods of 25% duty cycle
separated by 90µs, followed by a 90µs refractory period. In either case
the transmission of a single bit takes 250µs. Only the falling edge of the
clock signal is moved to alter the duty cycle. This leaves a pristine rising
edge for the acquisition module to use as the reference for its PLL clock
generator. A higher level protocol organizes commands as groups of 8
bits.
Data from the acquisition module is packed into 257 bit NRZ frames.
The idle state of the receive line is high. The first bit of each packet is a
zero and serves as the packet start bit. As with a UART, the start bit is
discarded. The following 256 bits are received into a 16 word x 16 bit
buffer for use by the StrongARM. The receive logic then looks for an idle
period (analogous to a UART stop bit) of at least 128µs in length as an
indicator that the link is again idle. Special marker words are inserted
into the ECG data packet (words 5, 9 and 13) to guarantee there will
never be a run of more than 80 bits of one's (or zeros), so there is no
possibility of satisfying the idle period requirement in the middle of a
data packet. Because the acquisition module clock is supplied by the
FPGA, receive bit timing errors are limited to phase uncertainty. By
searching for the beginning of the start bit in a fashion similar to that
used by UARTs the phase uncertainty is eliminated and the remainder
of the packet may be received without further synchronization. In
practice, the FPGA uses every edge in the receive data stream to re-sync