GE MAC 5000, Field Service Manual

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Revision B 5-8
CPU Theory of Operation: Theory of Operation
MAC 5000 resting ECG analysis system
2000657-002
Video Waveform Scrolling There are numerous ways of achieving this effect, none of which is
supported by standard LCD controllers. MAC 5000 achieves scrolling
through FPGA hardware placed between the LCD controller output and
the LCD panel input.
To achieve the scrolling effect it is necessary to maintain two virtual
image planes, one atop the other. Static (stationary) objects are drawn
in the static plane, which appears nearest the viewer and may be either
opaque or transparent. Dynamic (scrolling) objects are drawn in the
dynamic plane, which appears behind the static plane and is always
opaque, though not necessarily visible. The appearance of motion is
achieved by constantly changing the start point for display of the
dynamic plane from one display frame to the next.
Since the LCD controller does not support multiple image planes, it is
necessary to pack two planes of image data into a single frame buffer.
On the software side (during drawing) this is done by bit masking
operations that allow separate manipulation of two virtual pixels in each
byte of frame buffer memory. Each 8-bit byte holds a pair of pixels, one
from the static plane and one from the dynamic plane.
On the hardware side, part of each frame buffer byte (the static plane) is
played directly into the LCD after suitable color mapping. The
remainder of the frame buffer byte (the dynamic plane) is stored in a 1
line temporal buffer before being displayed. The amount of delay
applied to the line buffer before merging it with the static image data
determines it’s placement on the screen. By gradually changing the
delay, the dynamic image can be made to scroll.
In MAC 5000, each byte of frame buffer data is divided into a 5-bit field
for the static plane and a 3-bit field for the dynamic plane. This provides
a palette of 2^3=8 colors for dynamic objects and (2^5)-1=31 colors for
static objects (1 of the colors is transparent, leaving 31 real colors). In
practice, to be able to "freeze" dynamic objects requires that the 8
dynamic colors be replicated in the static color map, so there are
actually only 31-8=23 new colors available for static objects. The FPGA
implements a writeable color lookup table (CLUT) to map the pixel
values to sensible colors on the LCD. The CLUT provides 32 24-bit
entries, providing access to the complete color space offered by the LCD
panel.
LCD data is also fed to three external discrete 6-bit DACs to create video
for an external CRT. The horizontal and vertical sync pulses from the
LCD controller are combined to produce a composite sync signal which
is added to the green video. The FPGA’s asymmetric output drive
current (stronger pulldown than pullup) makes it difficult to source
video DAC currents directly into a 75
Ω
video cable. To allow the FPGA
to sink rather than source the video DAC currents, the video output is
referenced to the 3.3V supply rail and then level shifted back down to
ground by emitter followers. The DC level is restored by a second set of
emitter follower clamps referenced to two diode drops above ground. By
using dual transistor packs of the same type, temperature and process
drift are minimized.