Section 19 - Appendix B–Filter Board Options PWA 79562-01 and PWA 105521-01
77
13. Calculate
D
with
f
CLK
= 1 MHZ.
200
=
125
×
40
1000000
=
D
There is not a match for
D
= 200 within ±1 in the Divider Ratio Table so select
f
CLK
= 500 kHz.
14. Calculate
D
with
f
CLK
= 500 kHz.
100
=
125
×
40
500000
=
D
There is a match for
D
= 99 in the Divider Ratio Table. This is within ±1, so select
f
CLK
= 500 kHz.
15.
Set the divider ratio,
D
, jumpers that correspond to the divider ratio
D
= 99. Use
the Divider Ratio Table to set
D
.
On the Filter Board
Install:
W62,W63,W66, and W67
Remove:
W64 and W68
16. Set the input clock frequency,
f
CLK
, jumpers that correspond
f
CLK
= 500 kHz. Use the
Switched Capacitor Filter Input Clock Jumper Table to set
f
CLK
.
On the Filter Board
Install:
W9,W90
Remove:
W2,W7,W8,W10,W89
17. The filter for channel B is now completely configured. Configure channel A as
required and then verify the filter settings as described in
Section 19.15
.
