Interface
5-18
C141-E145-02EN
D*:
The command is addressed to the master device, but both the master device
and the slave device execute it.
X:
Do not care
5.3.2 Command descriptions
The contents of the I/O registers to be necessary for issuing a command and the
example indication of the I/O registers at command completion are shown as
following in this subsection.
Example: READ SECTOR(S)
At command issuance (I/O registers setting contents)
Bit
7
6
5
4
3
2
1
0
1F7
H
(CM)
0
0
1
0
0
0
0
0
1F6
H
(DH)
x
L
x
DV
Head No. / LBA [MSB]
1F5
H
(CH)
Start cylinder address [MSB] / LBA
1F4
H
(CL)
Start cylinder address [LSB] / LBA
1F3
H
(SN)
Start sector No. / LBA [LSB]
1F2
H
(SC)
Transfer sector count
1F1
H
(FR)
xx
At command completion (I/O registers contents to be read)
Bit
7
6
5
4
3
2
1
0
1F7
H
(ST)
Status information
1F6
H
(DH)
x
L
x
DV
Head No. / LBA [MSB]
1F5
H
(CH)
End cylinder address [MSB] / LBA
1F4
H
(CL)
End cylinder address [LSB] / LBA
1F3
H
(SN)
End sector No. / LBA [LSB]
1F2
H
(SC)
X’00’
1F1
H
(ER)
Error information
Summary of Contents for MHR2010AT
Page 1: ...C141 E145 02EN MHR2040AT MHR2030AT MHR2020AT MHR2010AT DISK DRIVES PRODUCT MANUAL ...
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Page 58: ...Theory of Device Operation 4 6 C141 E145 02EN Figure 4 3 Circuit Configuration ...
Page 188: ...Interface 5 114 C141 E145 02EN g d f f d e Figure 5 7 Normal DMA data transfer ...
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