Fujitsu MCM3064SS, Product Manual

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7.6 Bus Phases
C156-E228-02EN 7-25
Deskew Delay
×
2 (Min)
Deskew Delay
×
2 (Min)
Bus Clear Delay + Bus Settle Delay (Min)
Figure 7.12 RESELECTION phase
(2) Response sequence
When the SCSI device (INIT) detects that the SEL signal, I/O signal and data bus
bit (DBn) corresponding to the own SCSI ID are true and the BSY signal is false
for Bus Settle Delay or more, the INIT shall recognize that the INIT itself is
selected in the RESELECTION phase. At this time, the selected INIT performs
sampling to identify the SCSI ID of the TARG that requests the reconnection.
The INIT shall respond to the TARG by asserting the BSY signal within Selection
Abort Time.
When other than 2-bit SCSI ID is detected or when the parity error is detected on
the system in which the parity bit of the data bus is valid, the INIT shall not
respond to the RESELECTION phase.
After the TARG detects the response (BSY signal) from the INIT, the TARG
asserts the BSY signal, then release the SEL signal after Deskew Delay
×
2 or
more. After this time, the TARG may change the I/O signal state and data bus
value.
When the INIT detects that the SEL signal is false, the INIT stops sending the
BSY signal.