MB91F465XA EMULATION
Chapter 5 Appendix
MCU-AN-300015-E-V11
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© Fujitsu Microelectronics Europe GmbH
Bit
Name
Function
Bit 4
RCLK:
RAM Clock Selection
This bit selects the RAM clock in MB88121A,
MB88121B.
If this bit is “0”, the system clock is selected as the
RAM clock.
If this bit is “1”, the system clock divided by 2 is
selected as the RAM clock.
<<Note>>
When FlexRay controller can receive or transmit
data, these bits must not be changed.
Bit 3 – Bit 2
PMUL[1:0]:
PLL Multiplier Selection
These bits control the PLL multiplier. These bits
must set up so that the PLL clock is set to 80MHz.
For MB88121B, the evaluation of the PLL
performance is pending. For this reason, do not use
other settings than PMUL[1:0] = “11”.
PMUL[1] PMUL[0] Function
0
0
X0/X1 (4MHz) x 20
(80MHz) (tbd)
0
1
X0/X1 (5MHz) x 16
(80MHz) (tbd)
1
0
X0/X1 (8MHz) x 10
(80MHz) (tbd)
1
1
X0/X1 (10MHz) x 8
(80MHz)
<<Note>>
These bits must be changed before PON bit is set to
“1”.
Bit1
SSEL:
System Clock
Selection
This bit selects the system clock.
"0": Select the clock of X0/X1
"1": Select the clock of PLL
In MB88121 and MB88121A, the functionality of the
PLL is not guaranteed.
<<Note>>
•
Must be changed into "1" from "0" after "1" is
set as a PON bit and PLL lock-up time
(600us) passes.
•
If the oscillator of PLL is stopped, PON bit is
set to "0" after this bit is changed to "0".
•
When FlexRay controller can receive or
transmit data, these bits must not be
changed.
