MB91F465XA EMULATION
Chapter 5 Appendix
MCU-AN-300015-E-V11
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© Fujitsu Microelectronics Europe GmbH
DMA SUPPORT REGISTER (DMAS)
The DMA support register is available only in MB88121A/B. It is reserved in MB88121.
RSV
15
3
R
DMAOE
bit0
0
1
Initial value
0x00000000
DMAINV
2
R/W
High-Z
DMA Request Pin Output Enable
Output DMA Request
DMARE
bit1
0
1
DMA Request Enable
Disabled
Enabled
DMAOE
0
R/W
DMARE
1
R/W
DMAINV
bit2
0
1
DMA Request Level Inverted
Active level for DMA request is “H”
Active level for DMA request is “L”
RSV
bit31 - bit3
Reserved
Write “0”. “0” is read.
R:
R/W:
Read only
Read/Write
Bit
Name
Function
Bit 15 – 3
RSV: Reserved
These bits are reserved. "0" is read. Write "0".
Bit 2
DMAINV:
DMA Request Level
Inverted
This bit controls the DMA request level.
"0": Active level for DMA request is "H"
"1": Active level for DMA request is "L"
<<Note>>
It is valid when DMAOE bit is "1".
Bit 1
DMARE:
DMA Request enable
This bit controls the DMA request.
"0": Disabled
"1": Enabled
<<Note>>
It is valid when DMAOE bit is "1".
Bit 0
DMAOE:
DMA Request Pin
Output Enable
This bit controls output enable for DMA request pin.
"0": High-Z at DMA_REQ pin
"1": Output DMA request at DMA_REQ pin
Table 5-4: DMAS Register bit description