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P5F97/P5F103 User’s Manual
VGA Frame Buffer:
When set to “Enabled”, a fixed VGA frame
buffer from A000h to BFFFh and a CPU-to-PCI write buffer are
implemented. the options are “Enabled” (default) and “Disabled”.
Data Merge:
This option set the word-merge feature for the frame
buffer cycles. When “Enabled”, this controller checks the eight CPU
Byte Enabled signals to determine if data words read from the PCI
bus by the CPU can be merged. The default setting is “Disabled”.
Passive Release:
When set to “Enabled”, CPU-to PCI bus accesses
are allowed during passive release. When set to “Disabled”, only
PCI bus-master access to local DRAM is allowed during passive
release.
ISA Line Buffer:
The PCI to ISA Bridge has an 8-byte bi-
directional line buffer for ISA or DMA bus master memory reads
from or writes to PCI bus. When “Enabled”, an ISA or DMA bus
master can prefetch two doublewords to the line buffer for a read
cycle. The default is “Enabled”. The other option is “Disabled”.
Delayed Transaction:
This termination is used by targets that can’t
complete the initial data phase within the requirement of this
specification. One advantage of a Delay Transaction is that the bus
is not held in wait states while completing an access to a slow
device. While the originating master rearbitrates for the bus, other
bus masters are allowed to use the bus bandwidth that would
normally be wasted holding the master in wait states. Another
advantage is that all posted memory write data is not required to be
flushed before the request is accepted. Chipset has an embedded 32-
bit post write buffer to support delay transactions cycles. Select
“Enabled” to support compliance with PCI specification version 2.1.
AT Bus Clock:
You can set the speed of the AT bus in the terms of a
fraction of the CPU clock speed (CLK2). The options are “CLK2/2”,
“CLK2/3”, “CLK2/4”, “CLK2/5”, “CLK2/6” and “7.16MHz”. The
default setting is “CLK2/4”.
Chapter 3: BIOS Configuration
