P5F97/P5F103 User’s Manual
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DRAM Data Integrity Mode:
The options are “ECC” and “Parity”
and “Disabled”. Set to “ECC” or “Parity” only when DIMM
modules with parity bits are used. “ECC” will enable the Error
Checking and Correction function to ensure the DRAM data
integrity.
Host Read DRAM Command Mode:
The options are “Syn.” or
“Bypass”. This option sets type of Host Read DRAM Command
Mode.
SDRAM Burst X-1-1-1-1-1-1-1:
The options are “Disabled” and
“Enabled”. This feature set the DRAM Back-to-back burst read/
write timing. This timing depends on performance parameters of
installed memory chips (DRAM). The default setting is “Disabled”.
Pipelined Function:
When set to “Enabled”, the controller signals
of the CPU will latch a new memory address before all data
transfers for the current cycles are complete, resulting in a faster
performance.
Memory Hole At 15M-16M:
The default setting is “Disabled”. Set
to “Enabled” means that when the system memory size is equal to or
greater than 16M bytes, the physical memory address from 15M to
16M will be passed to PCI or ISA and there will be 1MBytes hole in
your system memory. This option is designed for some OS with spe-
cial add-in cards which need 15M-16M memory space.
I/O Recovery Period:
This option sets the delay between back-to-
back 8-bit and 16-bit I/O instructions. The options are “0us” and
“1us”. The default setting is “1us”.
Graphics Aperture Size:
This option determines the effective size
of the AGP Graphic Aperture, which memory-mapped graphic data
structures can reside in. The options are “16M”, “32M”, “64M”,
128M” and “256M”. The default is “64M”.
Primary Frame Buffer:
This option selects the size of PCI frame
buffer. The size of the buffer should not impinge on local memory.
The options are “All”, “1M”, “2M”, “4M”, “8M”, “16M” and
“Disabled”.
Chapter 3: BIOS Configuration
