P5F97/P5F103 User’s Manual
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memory modules come with parity bits and the option “DRAM Data
Integrity Mode” in the Chipset Features Setup has to be set to “ECC”.
EDO DRAM is designed to improve the DRAM read performance. It
holds the memory data valid until the next memory access cycle,
unlike FPM DRAM that tri-states the memory data when the
precharge cycle occur, prior to the next memory access cycle.
SDRAM uses the system clock to synchronize the flow of addresses,
data, control and the pipelining of operation. This yields a significant
memory performance improvement.
1.8 Accelerated Graphics Port (AGP) Slot
The P5F97/P5F103 mainboard is equipped with an Accelerated
Graphic Port slot which is compliant to the AGP specification 1.0. The
AGP runs at 66.6MHz (or 60MHz) clock and supports both 1x and 2x
mode for 66.6MHz and 133MHz 3.3V devices. The data transfer rate
on the AGP bus can be 4 times faster than PCI bus.
The following is a clock frequency for different system clock
operating modes:
System Clock
CPU Bus Clock
AGP Clock
PCI Clock
60MHz
60MHz
60MHz
30MHz
66MHz
66MHz
66MHz
33MHz
75MHz
75MHz
60MHz
30MHz
83MHz
83MHz
66MHz
33MHz
95MHz
95MHz
63MHz
31MHz
100MHz
100MHz
66MHz
33MHz
105MHz
105MHz
70MHz
35MHz
110MHz
110MHz
73MHz
36MHz
115MHz
115MHz
76MHz
38MHz
120MHz
120MHz
80MHz
40MHz
Chapter 1: Introduction
