2.7.1 PCI Express support
On the RDB, lanes A and C are configured as two independent x1 PCI Express
interfaces. These interfaces are compliant with the PCI Express Base Specification
Revision 2.0. The physical layer of the PCI Express interface operates at a transmission
rate of 3.125 Gbaud (data rate of 2.5 Gbit/s) per lane. The theoretical unidirectional peak
bandwidth is 2.5 Gbit/s per lane. Receive and transmit ports operate independently,
resulting in an aggregate theoretical bandwidth of 5 Gbit/s per lane. It supports Root
complex (RC) and End point (EP) configurations.
2.7.2 SGMII support
On the T1023RDB-PC, lane B of SerDes are used in 2.5G SGMII mode and lane D are in
1G SGMII mode. The Serial gigabit media independent interface (SGMII) is a high-
speed interface linking the Ethernet controller with an Ethernet PHY. SGMII uses
differential signalling for electrical robustness. Only four signals are required: receive
data and its inverse, and send data and its inverse.
2.7.3 SerDes clock
The clocking for the SerDes interface is 100 MHz for SerDes PLL1 and 125 MHz for
SerDes PLL2, both are provided by the 5P49V5901A616NLGI clock chip.
2.8 EC1 10/100/1000 BaseT interface (ETH1)
EC1 is set to operate in RGMII mode. It connects to a Realtek RGMII PHY
(RTL8211FS), as shown in the below figure.
EC1
EMI1
T1023
RGMII
MDC, MDIO
RTL8211FS
GBE PHY
MDIO PHY
Address = 1
RJ-45 Port
ETH1
Figure 2-4. RGMII interface connection
EC1 10/100/1000 BaseT interface (ETH1)
QorIQ T1023 Reference Design Board User Guide, Rev. 0, 08/2015
16
Freescale Semiconductor, Inc.
Summary of Contents for QorIQ T1023
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