2.1 Processor
The T1023RDB supports many features of the T1023 processor, as detailed in the
following sections. The boards and the supporting hardware are all identical, but the
ability to use various features depends on the device installed.
2.2 Power
The power supply system of the T1023RDB systems uses external power a12 V
for the RDB board. The rated power is 60 W.
• PoE Power Supply - Linear Technical LTC4269 on board is used for Power over
Ethernet function. It is compliant to the 802.3 at standard and can supply 22.5 W
power for the board. LTC4269 is sourced from the ETH3 ethernet port. Mini-PCIe
slot and SGMII PHY, AQR105 and USB regulators can be turned off by resetting
jumpers, once the PoE power is not enough. DCDC provides power these devices.
For more details, see
Connectors, Headers, Push buttons, and LEDs
• CPU VDD (DCDC_1V0) - The CPU core voltage
DCDC_1V0
rail is sourced from a
Linear switching regulator. The device used on the RDB is the LT8612.
DCDC_1V0
=
1.0 V.
• AVDD For Core PLL, Platform, SerDes - All these pins are sourced from VR500
SW2 output
VR500_1V8
, and RC filter is used for each pin. Voltage is 1.8 V.
• DDR - The memory interface power (VPP, VTT, GVDD, and VREF) are sourced
from VR500. VR500_2V5 for VPP = 2.5 V, VR500_VTT for VTT = 0.6 V,
VR500_1V2 for GVDD = 1.2 V, and VR500_VREF for VREF = 0.6 V.
• SerDes - The SerDes Receiver power S1VDD is sourced from a Linear regulator
LT3021. The SerDes Transmitter and PLL power X1VDD is sourced from the
VR500. LDO_1V0 for S1VDD = 1.0 V; VR500_1V35 for X1VDD = 1.35 V.
• eSPI, SDHC_WP, SDHC_CD (CVDD) - Each of these rails are sourced from the
VR500 SW2. VR500_1V8 for CVDD = 1.8 V.
• SD/MMC (EVDD) - EVDD can be selected between 1.8 V (VR500_1V8) and 3.3 V
(DCDC2_3V3), T1023 pin SDHC_VS is used to enable the selected rail. This pin is
pull down to select 3.3 V when it is set high, EVDD will be switched to 1.8 V rail.
• IFC, GPIO, JTAG IO, System Control (OVDD) - This rail is sourced from the
VR500 SW2. VR500_1V8 for OVDD = 1.8 V.
• I2C, UART (DVDD) - I2C and UART interface is operated in 3.3 V level, and are
sourced directly from the always on regulator LT8612 (U29), DCDC2_3V3 rail.
• Ethernet Interface, EMI1 EMI2 (LVDD/TVDD) - The LVDD rail is used for the
TSEC I/O and is configured for 1.8 V operation. The rail is sourced from VR500
SW2, rail is VR500_1V8. TVDD for EMI2 is 1.2 V and sourced from a linear
regulator LT3021, rail is LDO_1V2.
Power
QorIQ T1023 Reference Design Board User Guide, Rev. 0, 08/2015
12
Freescale Semiconductor, Inc.
Summary of Contents for QorIQ T1023
Page 1: ...QorIQ T1023 Reference Design Board User Guide Document Number T1023RDBUG Rev 0 08 2015...
Page 2: ...QorIQ T1023 Reference Design Board User Guide Rev 0 08 2015 2 Freescale Semiconductor Inc...
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