T1023
DDR4
Controller
MCS[0]_B
MCK, MCK_B, MCKE[0]
MRAS_B, MCAS_B, MWE_B
A[0:14], BA[0:1],BG[0:1]
MDQ[0:31]
MDQS[0:3], MDQS[0:3]_B
MDM[0:3]
ODT
PAR, ALERT, ACT
DDR4 Device
39 Ohm
VREF
VTT
Figure 2-3. DDR4 SDRAM connection
NOTE
DQ swap across nibbles is not allowed.
2.6 Termination
The DDR4 address, control, and command signals are terminated to the VTT rail through
39 Ohm resistor.
2.7 SerDes interfaces (PCIe/SGMII/SATA)
T1023 processor supports the SGMII, 2.5G SGMII and PCI Express high-speed I/O
interface standards. The table below details the SerDes connections.
Table 2-1. SerDes1 connectivity
SerDes Lane
Mode
Connected to
Comment
Lane A
PCI Express 1
Mini-PCIe slot
Used for WLAN type cards
Lane C
PCI Express 2
Mini-PCIe slot
Used for WLAN type cards
Lane B
2.5G SGMII
AQR105 PHY
Lane D
1G SGMII
Realtek SGMII PHY
Chapter 2 Architecture
QorIQ T1023 Reference Design Board User Guide, Rev. 0, 08/2015
Freescale Semiconductor, Inc.
15
Summary of Contents for QorIQ T1023
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