2.4 Clocks
The T1023 board uses single source clocking mode. The clock generator channel
provides 100 MHz to the system differential clock input. The Ethernet controller clock is
sourced from the RTL8211 PHY.
2.5 Memory interface
The memory interface on the RDB is configured as DDR4 and is implemented as a single
bank discrete chips (x8). ECC is not supported on the design. The memory size supported
on the board is shown below.
Figure 2-2. Memory interface
The PCB design is capable of running up to a clock rate of 800 MHz (1600 MT/s data
rate). The DDR4 interface uses the SSTL driver/receiver and 1.2 V power. A VREF,
1.2V/2 is needed for all SSTL receivers in the DDR4 interface. A VPP 2.5 V is need for
DDR4 which is used for activating power supply. For details on DDR4 timing design and
termination, see Application Note AN3940- Hardware and Layout Design Considerations
for DDR3 Memory Interfaces
. Signal integrity test results show this design does not
require serialing resistors (Series resistor (SR) and Termination resistor (TR)) for the
discrete DDR4 devices used. DDR4 supports on-die termination; the DDR4 chips and
T1023 are connected directly. The 1.2 V, VREF, VTT, and VPP are powered from a
PMIC VR500 output.
Clocks
QorIQ T1023 Reference Design Board User Guide, Rev. 0, 08/2015
14
Freescale Semiconductor, Inc.
Summary of Contents for QorIQ T1023
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