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Slide 64
Lab 3 – Internal Clock Source
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ICS Design Tips
When ICS is configured for FEE or FBE mode, input clock source must be
divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
Check the External and Internal Oscillator Characteristics Appendix for
electrical and timing specifications.
The external oscillator can be configured to provide a higher amplitude
output for noise immunity. This mode of operation is selected by HGO=1.
When switching modes of operation, if the newly selected clock is not
available, the previous clock will remain selected.
The TRIM and FTRIM value will not be affected by a reset.
