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Slide 63
Lab 3 – Internal Clock Source
ICS Application Code
// load trim value if location not blank
if (NVICSTRM != 0xFF) {
ICSTRM = NVICSTRM;
}
// output of FLL is selected, reference divider 1, internal reference clock selected
ICSC1 = 0x04;
// bus divider 2
ICSC2 = 0x40
Internal reference clock, FLL output, BDIV = 2,
fbus = (firc * 512 / BDIV) / 2
fbus = (32 kHz * 512 / 2) / 2 = 4.1 MHz bus
Note above settings are same as register default values. Optionally use scope to
monitor PWM output on J1-23.
